Hum pickup in PLL

Started by Andrew Holme in sci.electronics.design8 years ago 8 replies

I've completed layout of a PCB which includes a PLL which phase locks a VCXO to an external standard. I was planning on setting the PLL loop...

I've completed layout of a PCB which includes a PLL which phase locks a VCXO to an external standard. I was planning on setting the PLL loop bandwidth at a few Hz; but I'm worried that it won't be able to remove 50 Hz mains hum pickup. I would prefer not to electrostatically screen the circuit. It's all SMT on a 2-layer FR4 board with an almost continuous ground plane. The PLL circuit...


FRONT END WITH PLL

Started by RealInfo in sci.electronics.design8 years ago 7 replies

Hi all In a PLL contrlolled Rf amplifier front end how exactly the 1st RF stage frequency of the tuned circuit is contrlolled so it will be...

Hi all In a PLL contrlolled Rf amplifier front end how exactly the 1st RF stage frequency of the tuned circuit is contrlolled so it will be exactly the PLL freq+ IF frequncy ? Thanks EC


Fujitsu microcontroller (8-Bit) Clock Modes Problems

Started by Chris in sci.electronics.design9 years ago 7 replies
PLL

Hi, I'm programming on a Fujitsu Microcontroller from the MB95Fxxx family and I'm trying to switch the clock modes. (I'm using the MB95 So I...

Hi, I'm programming on a Fujitsu Microcontroller from the MB95Fxxx family and I'm trying to switch the clock modes. (I'm using the MB95 So I can switch from MAIN-PLL Clock to SUB-PLL Clock without any problems but I can not switch from SUB-PLL to MAIN-PLL correctly... I managed to isolate the prob: to switch the clock modes we only have 2 registers (SYCC (0x07) and PLLC (0x06)). If I re...


Lower time jitter in PLL

Started by Anonymous in sci.electronics.design9 years ago 13 replies
PLL

Hi, I have a litte problem with some measurements. I made a simple PLL (analog phase detector, active PI filter, loop filter bw=100 kHz, by...

Hi, I have a litte problem with some measurements. I made a simple PLL (analog phase detector, active PI filter, loop filter bw=100 kHz, by 8 prescaler) to multiply 10MHz from quartz generator to 80MHz. Signal from quartz generator had phase jitter ~ 0.76 mrad (10Hz-10kHz), from locked PLL ~ 1.17 mrad. Time jitter is definied as phase_jitter/(2*PI*carrier_freq), so for 10MHz ref. I got 12...


PLL with very high feedback clock and reference clock dividers

Started by bender in sci.electronics.design8 years ago 5 replies

I am trying to design a Charge pump PLL with very high feedback and reference dividers (around 2^15). The input clock is about 150 Mhz but the...

I am trying to design a Charge pump PLL with very high feedback and reference dividers (around 2^15). The input clock is about 150 Mhz but the output clock will be from 10-150 Mhz. If both N & M (dividers) values are around 30,000, the Phase detector checks the edges every 220 uS, i.e. the output pulse width is in the order 200uS when the PLL starts (Nanosim simulation).Since the output of th...


Switching loop filters of TSA5511 PLL

Started by megamusic in sci.electronics.design4 years ago

What is best way to switch time constants of loop filter in TSA5511 pll circuit (5-25V tuning voltage)? Can mosfet be used to switch on...

What is best way to switch time constants of loop filter in TSA5511 pll circuit (5-25V tuning voltage)? Can mosfet be used to switch on additional RC components?


low jitter PLL

Started by Anonymous in sci.electronics.design9 years ago 4 replies
PLL

dear all: what's the best low jitter PLL on the market? I want to achieve ~20-50 fs jitter from clock generator. $60 is okay. BR, Bigboy

dear all: what's the best low jitter PLL on the market? I want to achieve ~20-50 fs jitter from clock generator. $60 is okay. BR, Bigboy


RF Audio/Video modules

Started by jozamm in sci.electronics.design6 years ago 2 replies

Hi all, I have a pair of RF video modules and need some help to identify the model and maybe get the datasheet. There were given to me by a...

Hi all, I have a pair of RF video modules and need some help to identify the model and maybe get the datasheet. There were given to me by a friend of mine. They have no identification number except for the following - The frequency is selected by 4 DIP switches at both ends - The receiver has a LMX2331 2GHz PLL and an SL1461SA PLL FM demodulator - The receiver demodulates the audio as well...


Re: 24Hz to 60Hz PLL?

Started by krw in sci.electronics.design7 years ago 2 replies

On Sat, 20 Feb 2010 10:39:36 -0500, "Michael A. Terrell" wrote: > > Jim Thompson wrote: > > > > By 1967-68, when I was doing PLL, we...

On Sat, 20 Feb 2010 10:39:36 -0500, "Michael A. Terrell" wrote: > > Jim Thompson wrote: > > > > By 1967-68, when I was doing PLL, we already had quadrille pads. > > However we didn't yet have calculators... except for giant Philco > > on-desk machines bigger than today's towers ;-) > > > I went to a mall in Dothan, Alabama in 1972 or 73 while I was > statione


PLL Loop filter

Started by Andrew Holme in sci.electronics.design7 years ago 1 reply
PLL

This PLL loop filter is used with current-output charge-pumps: GND === .---. | .-| Z |-. ...

This PLL loop filter is used with current-output charge-pumps: GND === .---. | .-| Z |-. --- | '---' | --- | | i_N | ___ | |\ | --> ----o---|___|--o--|-\ | ___ | > -o--- --> ----o---|___|--o--|+/ i_P | | |/ --- ,---. --- | Z |


24Hz to 60Hz PLL?

Started by Chris in sci.electronics.design7 years ago 62 replies

I need to make a PLL that slaves to a 24Hz square wave. The output of the loop would be a 60Hz square wave. Any CMOS level chips that would be...

I need to make a PLL that slaves to a 24Hz square wave. The output of the loop would be a 60Hz square wave. Any CMOS level chips that would be good for this? I understand that I would need to divide by a decimal value of 2.5 for the loop. Thanks, Chris Maness


PLL Breadboard Issues

Started by Chris in sci.electronics.design7 years ago 15 replies
PLL

I bread boarded my PLL yesterday. I was able to get it to lock just fine on a multivibrator running at 33Hz. I was able to solve the jitter...

I bread boarded my PLL yesterday. I was able to get it to lock just fine on a multivibrator running at 33Hz. I was able to solve the jitter problem by using a very large value for C1 (1000u). However, when I attached my cameras to the loop, (one running at 22.2fps and the other running at 25fps) the loop would lock at a frequency slightly above the camera speed ~39Hz. The camera has a co...


FSK Radio design

Started by rich in sci.electronics.design6 years ago 83 replies

I am going around and around trying to design a solution for this radio. It is a single frequency radio (~1 GHz) FSK modulated at a high...

I am going around and around trying to design a solution for this radio. It is a single frequency radio (~1 GHz) FSK modulated at a high data rate (1 Mbps). I have the front end worked out but I am struggling with the demodulation. I understand that I can use a PLL to demodulate, as far as I can tell I would set the PLL at the carrier frequency and pick off the VCO voltage to obtain ...


that PLL again

Started by John Larkin in sci.electronics.design3 years ago 189 replies

I decided, interlaced with cooking and serving three sessions of turkey dinner, to simulate the 155.52 MHz PLL, the one that uses a 10 MHz...

I decided, interlaced with cooking and serving three sessions of turkey dinner, to simulate the 155.52 MHz PLL, the one that uses a 10 MHz reference and a d-flop bang-bang phase detector. The LT Spice thing is below, and here's a typical run: https://dl.dropboxusercontent.com/u/53724080/Circuits/PLLs/PLL_1.jpg The advantage to posting the screen shot is the insane Spice runtimes: it ...


PLL, measuring spurs etc

Started by Jan Panteltje in sci.electronics.design3 years ago
PLL

PLL, measuring spurs etc: http://panteltje.com/pub/ADF4350_via_mixer_2.4GHz_dBc_R820_tuner_fractional_all.gif I tested fractional mode on the...

PLL, measuring spurs etc: http://panteltje.com/pub/ADF4350_via_mixer_2.4GHz_dBc_R820_tuner_fractional_all.gif I tested fractional mode on the ebay ADF4350 evaluation board. I wanted dBc (relative to main carrier), did some coding on my xpsa spectrum analyzer. could well be wrong, but anyways, I only see the phase discriminator 100 kHz reference generated sidebands appear at -39 dBc, and...


Semi OT: History of consumer radio designs

Started by bitrex in sci.electronics.design3 years ago 14 replies

I'm interested in how the design of consumer AM/FM radios has evolved over time, particularly since digital tuning/ PLL synthesizers came on...

I'm interested in how the design of consumer AM/FM radios has evolved over time, particularly since digital tuning/ PLL synthesizers came on the scene. Some early (1980?) PLL receiver schematics I've seen show the LC front end tank being tuned by a varactor diode. I'd imagine for several reasons one would want to eliminate the complexity of this kind of front end setup if at all pos...


Wavetek 273

Started by Tim Wescott in sci.electronics.design6 years ago 32 replies

Anyone got any mileage, manuals, rumors, etc. of the Wavetek 273 signal generator? A customer is testing a PLL that I designed. The PLL is...

Anyone got any mileage, manuals, rumors, etc. of the Wavetek 273 signal generator? A customer is testing a PLL that I designed. The PLL is designed to go into the far sub-Hz bandwidths, and they're having trouble getting it to lock onto the 15kHz signal from a Wavetek 273. I've got it running off of a crystal oscillator divided down and made into a sine wave, and it's perking along ...


PLL and clock in altera cyclone 2 fpga

Started by Jamie Morken in sci.electronics.design9 years ago 1 reply

Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to...

Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to this block it will work properly, but the system clock is 27MHz which is too fast for the bit width's of the numerator and denominator even with pipelining selected in lpm_divide. I haven't used the cyclone PLL before, but its lowest output freq...


one-IC digital PLL?

Started by frank in sci.electronics.design1 year ago 15 replies

Hi all, I'm looking for a small-real-estate solution to generate a clock (ttl/cmos 5V) from a given quartz oscillator. The output clock I need...

Hi all, I'm looking for a small-real-estate solution to generate a clock (ttl/cmos 5V) from a given quartz oscillator. The output clock I need is 4/9 or 4/7 ratio of the original input clock. I know I can easily make a VCO/PLL solution, but the real problem is a very small space on the PCB, so I might be able to use a couple of small ICs, but probably not too much else. Input clock is < 2


FPGA as heater

Started by John Larkin in sci.electronics.design3 months ago 32 replies

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So, why not make an on-chip heater? Use a PLL to clock a bunch of flops, and vary the PLL output frequency to keep the chip temp roughly constant. -- John Larkin Highland Technology, ...