Lower time jitter in PLL

Started by Anonymous in sci.electronics.design10 years ago 13 replies
PLL

Hi, I have a litte problem with some measurements. I made a simple PLL (analog phase detector, active PI filter, loop filter bw=100 kHz, by...

Hi, I have a litte problem with some measurements. I made a simple PLL (analog phase detector, active PI filter, loop filter bw=100 kHz, by 8 prescaler) to multiply 10MHz from quartz generator to 80MHz. Signal from quartz generator had phase jitter ~ 0.76 mrad (10Hz-10kHz), from locked PLL ~ 1.17 mrad. Time jitter is definied as phase_jitter/(2*PI*carrier_freq), so for 10MHz ref. I got 12...


Switching loop filters of TSA5511 PLL

Started by megamusic in sci.electronics.design4 years ago

What is best way to switch time constants of loop filter in TSA5511 pll circuit (5-25V tuning voltage)? Can mosfet be used to switch on...

What is best way to switch time constants of loop filter in TSA5511 pll circuit (5-25V tuning voltage)? Can mosfet be used to switch on additional RC components?


PLL synthesizer chips

Started by Phil Hobbs in sci.electronics.design3 weeks ago 123 replies
PLL

Hi all, Since I'm feeling enough better to marshal a few brain cells together, I'm working on my third edition. We've been talking about...

Hi all, Since I'm feeling enough better to marshal a few brain cells together, I'm working on my third edition. We've been talking about PLLs off and on lately, so what are your fave high-performance PLL synthesizer chips, and why? I haven't used one since the MC14152, which I abandoned circa 1982. Thanks Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptic...


Possible PLL Lock Indicator?

Started by Jim Thompson in sci.electronics.design1 month ago 40 replies

Possible PLL Lock Indicator? (Assuming PFD) TD varied from 9.9ns to 10.1ns in 0.5ps Steps. Where you place the delay (inverters)...

Possible PLL Lock Indicator? (Assuming PFD) TD varied from 9.9ns to 10.1ns in 0.5ps Steps. Where you place the delay (inverters) would depend on if set-up-and-hold time of D-Flop's are positive or negative. Logic is _real_ 0.18um CMOS. ...Jim Thompson --


How does a PLL work?

Started by Piotr Wyderski in sci.electronics.design2 months ago 69 replies

But I mean, really. The usually presented theory is crystal-clear: There is a phase detector which produces voltage proportional to phase...

But I mean, really. The usually presented theory is crystal-clear: There is a phase detector which produces voltage proportional to phase difference of the input signals, which is then filtered and feed back to a VCO and the loop is closed. I am trying to implement a software PLL and my simulations show the above is not true. For zero phase difference the phase error voltage is also zero, ...


24Hz to 60Hz PLL?

Started by Chris in sci.electronics.design8 years ago 62 replies

I need to make a PLL that slaves to a 24Hz square wave. The output of the loop would be a 60Hz square wave. Any CMOS level chips that would be...

I need to make a PLL that slaves to a 24Hz square wave. The output of the loop would be a 60Hz square wave. Any CMOS level chips that would be good for this? I understand that I would need to divide by a decimal value of 2.5 for the loop. Thanks, Chris Maness


PLL Breadboard Issues

Started by Chris in sci.electronics.design8 years ago 15 replies
PLL

I bread boarded my PLL yesterday. I was able to get it to lock just fine on a multivibrator running at 33Hz. I was able to solve the jitter...

I bread boarded my PLL yesterday. I was able to get it to lock just fine on a multivibrator running at 33Hz. I was able to solve the jitter problem by using a very large value for C1 (1000u). However, when I attached my cameras to the loop, (one running at 22.2fps and the other running at 25fps) the loop would lock at a frequency slightly above the camera speed ~39Hz. The camera has a co...


FSK Radio design

Started by rich in sci.electronics.design6 years ago 83 replies

I am going around and around trying to design a solution for this radio. It is a single frequency radio (~1 GHz) FSK modulated at a high...

I am going around and around trying to design a solution for this radio. It is a single frequency radio (~1 GHz) FSK modulated at a high data rate (1 Mbps). I have the front end worked out but I am struggling with the demodulation. I understand that I can use a PLL to demodulate, as far as I can tell I would set the PLL at the carrier frequency and pick off the VCO voltage to obtain ...


that PLL again

Started by John Larkin in sci.electronics.design3 years ago 189 replies

I decided, interlaced with cooking and serving three sessions of turkey dinner, to simulate the 155.52 MHz PLL, the one that uses a 10 MHz...

I decided, interlaced with cooking and serving three sessions of turkey dinner, to simulate the 155.52 MHz PLL, the one that uses a 10 MHz reference and a d-flop bang-bang phase detector. The LT Spice thing is below, and here's a typical run: https://dl.dropboxusercontent.com/u/53724080/Circuits/PLLs/PLL_1.jpg The advantage to posting the screen shot is the insane Spice runtimes: it ...


PLL, measuring spurs etc

Started by Jan Panteltje in sci.electronics.design3 years ago
PLL

PLL, measuring spurs etc: http://panteltje.com/pub/ADF4350_via_mixer_2.4GHz_dBc_R820_tuner_fractional_all.gif I tested fractional mode on the...

PLL, measuring spurs etc: http://panteltje.com/pub/ADF4350_via_mixer_2.4GHz_dBc_R820_tuner_fractional_all.gif I tested fractional mode on the ebay ADF4350 evaluation board. I wanted dBc (relative to main carrier), did some coding on my xpsa spectrum analyzer. could well be wrong, but anyways, I only see the phase discriminator 100 kHz reference generated sidebands appear at -39 dBc, and...


Semi OT: History of consumer radio designs

Started by bitrex in sci.electronics.design3 years ago 14 replies

I'm interested in how the design of consumer AM/FM radios has evolved over time, particularly since digital tuning/ PLL synthesizers came on...

I'm interested in how the design of consumer AM/FM radios has evolved over time, particularly since digital tuning/ PLL synthesizers came on the scene. Some early (1980?) PLL receiver schematics I've seen show the LC front end tank being tuned by a varactor diode. I'd imagine for several reasons one would want to eliminate the complexity of this kind of front end setup if at all pos...


Wavetek 273

Started by Tim Wescott in sci.electronics.design6 years ago 32 replies

Anyone got any mileage, manuals, rumors, etc. of the Wavetek 273 signal generator? A customer is testing a PLL that I designed. The PLL is...

Anyone got any mileage, manuals, rumors, etc. of the Wavetek 273 signal generator? A customer is testing a PLL that I designed. The PLL is designed to go into the far sub-Hz bandwidths, and they're having trouble getting it to lock onto the 15kHz signal from a Wavetek 273. I've got it running off of a crystal oscillator divided down and made into a sine wave, and it's perking along ...


PLL and clock in altera cyclone 2 fpga

Started by Jamie Morken in sci.electronics.design9 years ago 1 reply

Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to...

Hi, I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to this block it will work properly, but the system clock is 27MHz which is too fast for the bit width's of the numerator and denominator even with pipelining selected in lpm_divide. I haven't used the cyclone PLL before, but its lowest output freq...


one-IC digital PLL?

Started by frank in sci.electronics.design2 years ago 15 replies

Hi all, I'm looking for a small-real-estate solution to generate a clock (ttl/cmos 5V) from a given quartz oscillator. The output clock I need...

Hi all, I'm looking for a small-real-estate solution to generate a clock (ttl/cmos 5V) from a given quartz oscillator. The output clock I need is 4/9 or 4/7 ratio of the original input clock. I know I can easily make a VCO/PLL solution, but the real problem is a very small space on the PCB, so I might be able to use a couple of small ICs, but probably not too much else. Input clock is < 2


FPGA as heater

Started by John Larkin in sci.electronics.design7 months ago 32 replies

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So, why not make an on-chip heater? Use a PLL to clock a bunch of flops, and vary the PLL output frequency to keep the chip temp roughly constant. -- John Larkin Highland Technology, ...


PLL Terminology Question

Started by Tim Wescott in sci.electronics.design5 years ago 68 replies
PLL

How commonly do you see PLL designs referred to as "type I", "type II", "type III", etc.? Do the terms make sense to you? I'm writing a...

How commonly do you see PLL designs referred to as "type I", "type II", "type III", etc.? Do the terms make sense to you? I'm writing a report; don't want to either baffle with bullshit nor leave out handy terms... -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wesco...


Trying to remember IC name

Started by bitrex in sci.electronics.design4 years ago 11 replies

I'm trying to remember the name of a certain IC. I believe it was a PLL-type frequency synthesizer IC for AM/FM radios, to be used with an...

I'm trying to remember the name of a certain IC. I believe it was a PLL-type frequency synthesizer IC for AM/FM radios, to be used with an external local oscillator. I'm fairly certain it had the prefix SA-something, so it was a former Signetics chip. I don't think it's still in production by NXP, though. Any ideas?


Frequency-to-voltage converter, PLL with an AD650

Started by Jean-Pierre Coulon in sci.electronics.design3 years ago 10 replies

I tried to reproduce fig.22, p.17 of the datasheet but the output voltage is always about +13 V The VCO alone (like fig.12) works up to about...

I tried to reproduce fig.22, p.17 of the datasheet but the output voltage is always about +13 V The VCO alone (like fig.12) works up to about 1 MHz provided the input voltage is in the [-12:0] range. Has anybody a working schematics? Regards, -- Jean-Pierre Coulon


RF in SOCs?

Started by Sonnich Jensen in sci.electronics.design2 years ago 21 replies

Hi guys I havent working with RF for ages, but am using it now. I know about "classic" radios, with coils for filters and OSCs. Now, with SOC...

Hi guys I havent working with RF for ages, but am using it now. I know about "classic" radios, with coils for filters and OSCs. Now, with SOC (system on chip) I dont need to know about it, but I still wonder - I can make an oscillator or PLL, not problem, but say the IF and filters on chip? What replaces the coil-filter in an SOC?


PLL -- basic question

Started by vkj in sci.electronics.design6 years ago 17 replies

I have just started reading about PLLs. Most of the (introductory) material I have seen always starts with the phase as the detected variable. ...

I have just started reading about PLLs. Most of the (introductory) material I have seen always starts with the phase as the detected variable. And phase = Integral(freq). But why not use frequency itself? That is, why cant you determine the frequency (using a counter) and compare that with the desired frequency and thus generate an appropriate error signal to the VCO? Thanks, vkj ...