pcb signal integrity check

Started by Anonymous in sci.electronics.design2 years ago

This is the control board of my alternator simulator. I think we are getting close to receiving a purchase...

This is the control board of my alternator simulator. I think we are getting close to receiving a purchase order! https://www.dropbox.com/s/wvyxwlwzou3thh9/T901_22.JPG?raw=1 It has high power, relay drivers, uP, FPGA, dram, ethernet, USB. It goes close to the front panel in this: https://www.dropbox.com/s/71whot11i312y63/P900_3d_3.jpg?raw=1 My homework assignment is to do the s...


FPGA as heater

Started by John Larkin in sci.electronics.design5 years ago 32 replies

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So, why not make an on-chip heater? Use a PLL to clock a bunch of flops, and vary the PLL output frequency to keep the chip temp roughly constant. -- John Larkin Highland Technology, ...


Apollo Guidance Computer - facts from the horses mouths

Started by Anonymous in sci.electronics.design2 years ago 16 replies

A few weeks ago there was a thread where ppl were citing 'facts' about design and implementation issues of the AGC. I had forgotten about this...

A few weeks ago there was a thread where ppl were citing 'facts' about design and implementation issues of the AGC. I had forgotten about this site...it should clear up some misunderstandings/flat out wrong assertions about the AGC. https://authors.library.caltech.edu/5456/1/hrst.mit.edu/hrs/apollo/public/conference3/intro.htm Some years ago I started doing a FPGA implementation o


dumb triangle oscillator

Started by John Larkin in sci.electronics.design6 years ago 28 replies

I'm designing a test set for an energy digitizer/integrator box. It has a 12-bit, 250 MHz ADC and an FPGA and stuff. We want to make sure...

I'm designing a test set for an energy digitizer/integrator box. It has a 12-bit, 250 MHz ADC and an FPGA and stuff. We want to make sure that every ADC bit works, and no data bits are shorted to other bits on the PC board. So we'll apply a triangle wave that's a bit bigger than the 0..+3 volt ADC range, randomly read values, and run some sort of code to make sure every bit goes up and d...


Symmetric DC-DC power transformer

Started by Anonymous in sci.electronics.design1 year ago 2 replies

I am working on a dual active bridges (4 mosfets instead of 4 diodes) by switching directions using either: 555, CPLD, FPGA or micro, depending...

I am working on a dual active bridges (4 mosfets instead of 4 diodes) by switching directions using either: 555, CPLD, FPGA or micro, depending on timing complexity. In the simplest case, just a 555 switching primary and secondary at the same time. In more complicated case, a micro switching with turn-on delay T1, turn-on time T2, turn-off delay T3 and frequency F1. What are the


DSP phase noise measurement with an SDR

Started by Andrew Holme in sci.electronics.design5 years ago 8 replies

I found this paper about measuring phase noise with just an ADC following by...

I found this paper about measuring phase noise with just an ADC following by DSP. http://jmfriedt.sequanux.org/phase_digital/grove_hein_tsc_direct_digital_PN_measurement.pdf I tried a simplified single channel experiment using an FPGA eval board: sig. gen. => ADC I = nco.cos() * ADC Q = nco.sin() * ADC I_baseband = CIC_LPF_Decimate(I) Q_baseband = CIC_LPF_Decimate(Q) angle = CORDIC


xilinx vivado and zynq

Started by Jon Kirwan in sci.electronics.design9 years ago 6 replies

I frankly haven't been keeping up and wasn't aware of the Zynq-7000 until receiving a notice about...

I frankly haven't been keeping up and wasn't aware of the Zynq-7000 until receiving a notice about this: http://www.cvent.com/events/x-tech-presented-by-xilinx-and-avnet/event-summary-cd148dbc1dc84db0b 03345f14fef5956.aspx And this interesting article about Vivado by Clive Maxfield: http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4371643 /Xilinx-unv


voltage drop on STRATIX FPGA supply planes

Started by coli...@yahoo.com in sci.electronics.design10 years ago 12 replies

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself,...

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself, let alone getting the power to the BGA which is dropping another 50mV. Surely the 30mV cannot be true as there is a power plane in the BGA package itself. Historically I would look at the size of the plane and assume that everything is fine and I c...


fast ADC, thermal image

Started by John Larkin in sci.electronics.design10 years ago 4 replies

Here's a little digitizer box http://dl.dropbox.com/u/53724080/Circuits/ESM/ESM_PCB.jpg and the thermal image of...

Here's a little digitizer box http://dl.dropbox.com/u/53724080/Circuits/ESM/ESM_PCB.jpg and the thermal image of same http://dl.dropbox.com/u/53724080/Circuits/ESM/ESM_IR.jpg The hot chip at the target is an LTC2242-12 12-bit ADC being clocked at 250 MHz. The bigger chip below is an Altera EP3C5F256 FPGA. What amazed me is that we can actually get reliable data at 250 MHz, and...