Test Fixture Failures

Started by rickman in sci.electronics.design5 years ago 11 replies

I have a test fixture that has been in use for some 8 years testing thousands of units. It is not a complex unit with a power supply section,...

I have a test fixture that has been in use for some 8 years testing thousands of units. It is not a complex unit with a power supply section, an FPGA, an RS-232 level converter chip, two RS-422 receiver/driver chips and various connectors for the UUT and test points. It is powered by a CUI wall wart bought from Digikey. It has worked very well over this time requiring a replacement of...


test gadget

Started by John Larkin in sci.electronics.design8 years ago 17 replies

Imagine a box with a USB interface, that is full of DACs, a mux'd high-quality DVM, a bunch of logic i/os, I2C and SPI, some SSRs, a...

Imagine a box with a USB interface, that is full of DACs, a mux'd high-quality DVM, a bunch of logic i/os, I2C and SPI, some SSRs, a few programmable power supplies, all easy to control from various programming languages. An internal FPGA would be programmable through the USB port. The standard config would do the standard i/o, but it would be user reprogrammable to do special stuff, w...


High speed pulse generator to test oscilloscope

Started by Anonymous in sci.electronics.design8 years ago 12 replies

Greetings I have a Tek TDS694C I will be selling, and I'd like to demo it's high speed performance by showing it detecting a rise time - I'm...

Greetings I have a Tek TDS694C I will be selling, and I'd like to demo it's high speed performance by showing it detecting a rise time - I'm trying to remember exactly what that is - somewhere in picosecnd range? Is there a chip which will show a fast rise time? I believe they use some kind of high speed fpga? thanks in advance jb


jitter on SPI interface and clock-domains

Started by kristoff in sci.electronics.design5 years ago 15 replies

Hi, I am currently again learning some more VHDL and the exercise project I am working on now is to implement SPI slave. This is to be used...

Hi, I am currently again learning some more VHDL and the exercise project I am working on now is to implement SPI slave. This is to be used in combination with a STM32F103 maple mini clone. Question. How much jitter can one expect on a SPI-interface between a MPU (in a breadboard) and a FPGA connected with jumper-wires? According the datashield of ST, the STM32F103 can do SPI a...


Sigma-Delta vs. Ramp

Started by Ricketty C in sci.electronics.design1 year ago 3 replies

I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of...

I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals. If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output.


Filter Evolution

Started by John Larkin in sci.electronics.design7 years ago

We're working on the FPGA signal processing for The Wayback Machine. This is a box that stores user-supplied waveform files and plays...

We're working on the FPGA signal processing for The Wayback Machine. This is a box that stores user-supplied waveform files and plays them back at some programmable rate. If we use a DDS clock to determine the playback sample rate, and dump the file data into a DAC, we get the obvious stairsteps in the data, at the sample rate SR. A sine wave at frequency Fs, which was sampled at, say,...


contract pcb layout

Started by John Larkin in sci.electronics.design10 years ago 75 replies

Hi, What are you guys paying these days for contract PCB layout? And as long as I'm asking, how about FPGA design? I'm getting...

Hi, What are you guys paying these days for contract PCB layout? And as long as I'm asking, how about FPGA design? I'm getting quotes in the $125 to $175/hour range. John ********************************** John Larkin, President Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picoseco...


T904 board

Started by John Larkin in sci.electronics.design2 years ago 5 replies

Here's another big board. https://www.dropbox.com/s/bfepc9wsaxwgs8p/T904_PCB_1.JPG?raw=1 This is the main part of a test set to production...

Here's another big board. https://www.dropbox.com/s/bfepc9wsaxwgs8p/T904_PCB_1.JPG?raw=1 This is the main part of a test set to production test a laser controller. Upper-left is a MicroZed, which is the compute/FPGA and communications bit. Upper right are a couple of the cute LTM switcher bricks. This connects to the DUT, an oscilloscope, a DVM, and a Keysight counter, so there's ...


Differential PWM filter

Started by bitrex in sci.electronics.design6 years ago 1 reply

Say I have 2 or 3 PWM channels coming out of a FPGA or microcontroller or something, and I want to filter and sum them into one analog...

Say I have 2 or 3 PWM channels coming out of a FPGA or microcontroller or something, and I want to filter and sum them into one analog output. Is there any advantage to using 4 or 6 output lines and using an opamp in a differential summer/two pole filter configuration, over using a single ended summer/filter?


ARM Cortex M4 filter calculations

Started by Spehro Pefhany in sci.electronics.design6 years ago 19 replies

Hi, Any idea roughly what clock frequency I would be looking at in order to have an ARM Cortex M4 do IIR filter calculations? I need maybe...

Hi, Any idea roughly what clock frequency I would be looking at in order to have an ARM Cortex M4 do IIR filter calculations? I need maybe 3E6 multiple/accumulates per second, so maybe capable of 10E6 per second with 100% usage. The M4 core offers a 32 bit multiply/64 bit accumulate in 1 cycle... This is to run four decimation filters in parallel. I don't want to use an FPGA. ...


testing an ADC

Started by John Larkin in sci.electronics.design3 years ago 8 replies

We have a product with a 12-bit ADC that's being clocked around 60 MHz, with the data poured into an FPGA. We want to do a good production...

We have a product with a 12-bit ADC that's being clocked around 60 MHz, with the data poured into an FPGA. We want to do a good production test. We can route a big triangle wave into the adc and take a lot of samples. Our thinking is that each bit should be high about 50% of the time, and we can set limits on that. This will catch bits stuck high or low, bits shorted to other bits, ope...


Bar Code Labeling Software

Started by rickman in sci.electronics.design8 years ago 20 replies

I need to label some packages I will be shipping, both the bags the boards are in and the boxes. There will be several fields on the labels...

I need to label some packages I will be shipping, both the bags the boards are in and the boxes. There will be several fields on the labels and each field has a bar code, CODE128. I may also try to label the individual boards, but there isn't much room for a label, maybe on top of the FPGA. I found some software that is supposed to work with Open Office, but I haven't figured out quit...


sin3 filter for delta-sigma

Started by John Larkin in sci.electronics.design2 years ago 20 replies

If I use an isolated delta-sigma modulator, like a TI AMC1306 or something, to pick off the signal on a current shunt, we'd build a sinc3...

If I use an isolated delta-sigma modulator, like a TI AMC1306 or something, to pick off the signal on a current shunt, we'd build a sinc3 filter into an FPGA to make the data stream into, say, 16 bit parallel form. The d-s converter would run at maybe 20 MHz, and I could probably get 16-bit digitizing with about 150 KHz equivalent bandwidth. If the sinc3 is (I think) essentially a FIR...


delta-sigma modulator in LT Spice

Started by Anonymous in sci.electronics.design2 years ago 8 replies

Here's a second-order delta-sigma modulator, approximating an ADUM7703 in LT Spice. I don't think the integration constants (currently 1 us)...

Here's a second-order delta-sigma modulator, approximating an ADUM7703 in LT Spice. I don't think the integration constants (currently 1 us) matter. Gotta think about that. The output filter will be of course digital, in an FPGA. I really want the net frequency response to be about 20 KHz, first order, so we'll probably use some fast sinc3 filter or something to mash the noise down, fol...


Supervisor/reset ICs

Started by bitrex in sci.electronics.design5 years ago 8 replies

Do you use some kind of supervisory/reset IC in all your microprocessor/FPGA projects? I've made small quantities of widgets using AVRs and...

Do you use some kind of supervisory/reset IC in all your microprocessor/FPGA projects? I've made small quantities of widgets using AVRs and haven't encountered any reliability problems just using the recommended RC/diode reset circuit in their material. I'm thinking about making larger quantities of widgets using AVRs and battery powered, and wondering if using a supervisor would be cheap...


transformer thermals

Started by Anonymous in sci.electronics.design1 year ago 54 replies

We can sense the primary current of this transformer, with a shunt and an isolated delta-sigma ADC. The FPGA squares the samples and...

We can sense the primary current of this transformer, with a shunt and an isolated delta-sigma ADC. The FPGA squares the samples and filters, so we can pick that up and square root to get RMS current. The tranny is rated for 240 VA, which would be 9.6 amps RMS in the primary. So I ran it for a few hours with 10 amps DC in the primary. Temp rise was about 26C in free air. I think people de...


Darlington driver interfaces with mixed voltages

Started by Bruce Varley in sci.electronics.design10 years ago 13 replies

I'm planning to use a ULN2003 7-way darlington driver as an input/output isolator for a FPGA with 3.3v I/O. The input interface has pullups from...

I'm planning to use a ULN2003 7-way darlington driver as an input/output isolator for a FPGA with 3.3v I/O. The input interface has pullups from the collectors to 3.3v supply, and the output base inputs are driven by the gate array output lines, and switch loads (relays and LEDs) to a 12vdc supply. Total i/o count is 6, so one 2003 will do the job, however I'm wondering whether the commo...


battery-backed SRAM

Started by John Larkin in sci.electronics.design5 years ago 50 replies

I'm designing a benchtop gadget that will uses a 7020 ZINQ SOC chip, which is an FPGA with two ARM cores on-chip. I want to save a...

I'm designing a benchtop gadget that will uses a 7020 ZINQ SOC chip, which is an FPGA with two ARM cores on-chip. I want to save a user's last setup when power fails, and restore it at powerup. The 7020 has on-chip batter-backed ram, but apparently only to store some encryption key, not for general use. So I need an external ram and a battery. Digikey offers exactly 4000 choices when I...


pot core

Started by John Larkin in sci.electronics.design6 years ago 69 replies

I designed a laser controller in 2002, and it's licensed to a contract manufacturer. Parts are headed for end-of-life. Old Xilinx FPGA, 68K CPU,...

I designed a laser controller in 2002, and it's licensed to a contract manufacturer. Parts are headed for end-of-life. Old Xilinx FPGA, 68K CPU, things like that. It has a custom transformer in the isolated dc/dc converter. https://dl.dropboxusercontent.com/u/53724080/Circuits/Power/TEM1_DCDC/28S910Dsh17.pdf https://dl.dropboxusercontent.com/u/53724080/Circuits/Power/TEM1_DCDC/XFMR_5.JP...


isolated delta-sigma converters

Started by John Larkin in sci.electronics.design2 years ago 31 replies

https://www.analog.com/en/products/adum7703.html#product-overview and the similar http://www.ti.com/product/AMC1106E05 This is cool. I...

https://www.analog.com/en/products/adum7703.html#product-overview and the similar http://www.ti.com/product/AMC1106E05 This is cool. I can hang a current shunt and a voltage divider on my transformer output, and the isolated delta-sigma data streams can go straight into an FPGA without an ADC. They need DC power on the isolated side, which is a minor nuisance. -- John Lark...