cmos delay vs temperature

Started by John Larkin in sci.electronics.design5 years ago 9 replies

I found one old Fairchild appnote that has some numbers https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/CMOS_Delay_Temp.pdf which...

I found one old Fairchild appnote that has some numbers https://dl.dropboxusercontent.com/u/53724080/Parts/Logic/CMOS_Delay_Temp.pdf which averages to around +3000 ppm/degC, or about +3 ps per ns of prop delay per degree C. That's with 50 pF loading, sorta high. This is HC, pretty old technology. I have a vague impression that the innards of a typical FPGA may be better. Here's a ri...


Genetic FPGA

Started by mixed nuts in sci.electronics.design6 years ago 37 replies

... "Dr. Adrian Thompson is a researcher operating from the Department of Informatics at the University of Sussex, and his experimentation in...

... "Dr. Adrian Thompson is a researcher operating from the Department of Informatics at the University of Sussex, and his experimentation in the mid-1990s represented some of science?s first practical attempts to penetrate the virgin domain of hardware evolution. The concept is roughly analogous to Charles Darwin?s elegant principle of natural selection, which describes how indiv


RMS jitter

Started by John Larkin in sci.electronics.design6 years ago 7 replies

I should know this, but it's easy to ask. Assume the rising edge of a pulse that is delayed from a trigger, and that has 1 ns p-p jitter...

I should know this, but it's easy to ask. Assume the rising edge of a pulse that is delayed from a trigger, and that has 1 ns p-p jitter relative to trigger, with a uniform probability distribution. We'd get that if we used a 1 GHz unsynchronized clock to generate the delay, which we're now doing in an FPGA. What is the RMS jitter? I recall there being something like a square root o...


Altera FPGA weirdness

Started by John Larkin in sci.electronics.design10 years ago 28 replies

Hi, We have a new board we just designed, and we're trying to fire up the first one. http://www.panoramio.com/photo/60806547 It has an...

Hi, We have a new board we just designed, and we're trying to fire up the first one. http://www.panoramio.com/photo/60806547 It has an Altera EP2AGX45DF29C5N on board; says so right on the label. When we hook up the JTAG USB Blaster pod and run the Quartus Programmer program, it insists that the chip is a GX65 so it doesn't allow us to load a configuration that was compiled for a GX...


Freescale fractional clock divider paper

Started by bitrex in sci.electronics.design4 years ago 24 replies

This looks interesting but I'm having trouble deciphering how it's actually supposed to work due to poor tech writing/diagramming on the part...

This looks interesting but I'm having trouble deciphering how it's actually supposed to work due to poor tech writing/diagramming on the part of the authors. Can anyone explain how this system is actually supposed to work or what a real-world FPGA implementation might look like?


digital I/Q

Started by John Larkin in sci.electronics.design3 years ago 17 replies

I want to measure the phase angle between two 100 MHz waveforms. One way to do that is to phase shift one of them 90 degrees and mix...

I want to measure the phase angle between two 100 MHz waveforms. One way to do that is to phase shift one of them 90 degrees and mix those two with the other, and lowpass the I and Q products. The filtered I and Q voltages plot a circle as a function of the phase difference, and the angle is the arctan of those two voltages. If I do all that inside an FPGA (except the analog filters) I'...


capacitor placement

Started by rob d in sci.electronics.design2 years ago 5 replies

Hi all. I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am...

Hi all. I am routing GBit FPGA links at 12GBit and I am having an issue with DC blocking capacitor placement with Ultrascale plus devices. I am new to the company and I am up against "we always do it that way". The closest I can get some of the caps is 13mm from the BGA pad but that causes horrendous other routing issues. Assuming the link is a sine wave then the "edge" takes 83p


FPGA

Started by John Larkin in sci.electronics.design4 years ago 30 replies

https://www.digikey.com/product-detail/en/xilinx-inc/XCVU440-3FLGA2892E/XCVU440-3FLGA2892E-ND/76 04556 -- John Larkin Highland...

https://www.digikey.com/product-detail/en/xilinx-inc/XCVU440-3FLGA2892E/XCVU440-3FLGA2892E-ND/76 04556 -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com


PRBS in LT Spice

Started by John Larkin in sci.electronics.design9 years ago 25 replies

We are considering sending data over CAT6 twisted-pairs, from one FPGA to another at some 10s of meters distance. It might be prudent...

We are considering sending data over CAT6 twisted-pairs, from one FPGA to another at some 10s of meters distance. It might be prudent to transformer-couple the data, to avoid ground-loop common-mode hazards, and the obvious choice would be to use RJ45 connectors with built-in Ethernet magnetics. These seem to have inductance in the 400 uH range, which gives a low-end frequency response in t...


Microsemi FPGAs

Started by John Larkin in sci.electronics.design4 years ago 2 replies

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or...

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or dislikes? They look like a pretty good deal for a medium FPGA with ARM. -- John Larkin Highland Technology, Inc lunatic fringe electronics


Kanerva on "Computing with 10,000-Bit Words"

Started by Joe Gwinn in sci.electronics.design4 months ago 5 replies

This article from 2014 is Kanerva's 7-page summary of the then current state of Sparse Distributed Memory, Spatter Codes, and related...

This article from 2014 is Kanerva's 7-page summary of the then current state of Sparse Distributed Memory, Spatter Codes, and related areas, with an extensive reference list. The computational engine Kanerva describes here is something that the denizens of S.E.D. could implement in a small FPGA, should it be useful to do so. A likely use would be content-addressed memory that can tolera...


Looking for SMD level shifters to TTL

Started by John Robertson in sci.electronics.design3 months ago 25 replies

Working on a FPGA project and we need perhaps 30 level shifter gates. Anyone work with 3.6 to 5.0 volt interfaces that can recommend any...

Working on a FPGA project and we need perhaps 30 level shifter gates. Anyone work with 3.6 to 5.0 volt interfaces that can recommend any single part over the rest before I spend a few hours digging through Digi/Mouser/Newark's inventory? In some cases we can get away with resistors, but there is a bit of TTL level drivers needed. Thanks! John :-#)# -- (Please post followups or...


1x2 DVI Splitter

Started by zorbey in sci.electronics.design9 years ago 5 replies

Hello All, Can you comment on how to realize a 1x2 DVI splitter? Do you know any specific circuits or ICs? If not, can you comment on how to...

Hello All, Can you comment on how to realize a 1x2 DVI splitter? Do you know any specific circuits or ICs? If not, can you comment on how to realize this using programmable stuff like FPGA or CPLDs? Any device recommendation for this? Thanks and Best Regards G=F6khan =D6zcan


PCB Testing after Design

Started by Anonymous in sci.electronics.design7 years ago 12 replies

Hi, I'm a newbie when it comes to hardware design. I have a little bit of exper= ience with PCB design and made a couple of small circuits for...

Hi, I'm a newbie when it comes to hardware design. I have a little bit of exper= ience with PCB design and made a couple of small circuits for learning purp= oses. I need to test out this new PCB designed by another person and its ki= nd of a complicated board with a ton of components on it. It consists of an= ADC and an FPGA and other components that go along with it. It's really si= mil...


dumb design, happy ending

Started by John Larkin in sci.electronics.design8 years ago 7 replies

I designed a 48-channel optoisolated digital input module, something having to do with a submarine. The customer wanted built-in-self-test,...

I designed a 48-channel optoisolated digital input module, something having to do with a submarine. The customer wanted built-in-self-test, so I did this: https://dl.dropboxusercontent.com/u/53724080/Optos/V280_channel.JPG The idea is to transformer-couple in a positive pulse and force the opto on, then a negative pulse to force it off, and check those in the FPGA. The original pulse ...


new board

Started by John Larkin in sci.electronics.design10 years ago 2 replies

http://dl.dropbox.com/u/53724080/Circuits/V545_A.JPG It's a 24-channel synchro/LVDT simulator/acquisition thing, in VME format. It's *heavy*...

http://dl.dropbox.com/u/53724080/Circuits/V545_A.JPG It's a 24-channel synchro/LVDT simulator/acquisition thing, in VME format. It's *heavy* from all the plugin transformers. BGA FPGA and ARM chips, all on 6 layers. All we have to do now is make it work. -- John Larkin, President Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com ...


polymer aluminum cap

Started by John Larkin in sci.electronics.design9 years ago 23 replies

I designed a 0.9 volt power supply using LTM8023 switcher bricks, and used an aluminum bulk filter cap. It turns out to have too much...

I designed a 0.9 volt power supply using LTM8023 switcher bricks, and used an aluminum bulk filter cap. It turns out to have too much ESR, and I got a lot of output ripple, 0.6 volts p-p at 1/3 the switching frequency, some weird sub-cycle oscillation. It only started oscillating as my customer kept adding more and more code to the FPGA, increasing core current. There are two fixes: incre...


Spicing pcb traces

Started by John Larkin in sci.electronics.design3 years ago 16 replies

My new pulse generator has more trigger jitter than I'd like, so I'm investigating the front end. There's a fast comparator that gets...

My new pulse generator has more trigger jitter than I'd like, so I'm investigating the front end. There's a fast comparator that gets the external trigger, makes differential PECL out, a DPDT switch for edge inversion, and that goes into the diff clock input of an FPGA. The layout is mediocre: see the red traces. https://www.dropbox.com/s/l72583wohvi2vf3/Trig_Traces_2.jpg?dl=0 LT Spi...


SOT-23 at 1.5 watts

Started by John Larkin in sci.electronics.design5 years ago 22 replies

I'm designing an LDO to drop 1.8 volts to 1.0, to power an FPGA core. We have a SOT23 n-channel mosfet in stock, IRLML6344. IR rates it at 1.3...

I'm designing an LDO to drop 1.8 volts to 1.0, to power an FPGA core. We have a SOT23 n-channel mosfet in stock, IRLML6344. IR rates it at 1.3 watts power dissipation, and I was skeptical, because a SOT23 is usually good for maybe 300 mW and IR is notoriously optimistic in their power specs. But it can dissipate 1.5 watts somehow. https://dl.dropboxusercontent.com/u/53724080/Parts/Fets...


transmission line Colpitts oscillator

Started by John Larkin in sci.electronics.design3 years ago 12 replies

I've been thinking about this https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0 as a roughly 500 MHz clock oscillator for...

I've been thinking about this https://www.dropbox.com/s/yuu737wb3cqizph/TX_Line_Osc_3.JPG?dl=0 as a roughly 500 MHz clock oscillator for some digital stuff. My FPGA guys claim they can accept that as an LVDS clock input. The comparator would be LVDS in and out, FAN1101 maybe, if it is really fast enough. So I have a question for some more RF-ey guys than me. Q1 furnishes negative r...