Hardware Based IP Protection

Started by Ricky in sci.electronics.design2 months ago 43 replies

A customer wants me to redesign a board to eliminate the production bottlenecks. They also want all IP so they can make the boards themselves if...

A customer wants me to redesign a board to eliminate the production bottlenecks. They also want all IP so they can make the boards themselves if my company is unable to. I'm fine with that, but I'd like to have some means of assurance they won't make boards without my royalty being respected. The board has an FPGA which contains the "magic", an analog path, and a digital path


really slow PLL

Started by John Larkin in sci.electronics.design4 months ago 172 replies

Suppose I have several rackmount boxes and each has a BNC connector on the back. Each of them has an open-drain mosfet, a weak pullup, and...

Suppose I have several rackmount boxes and each has a BNC connector on the back. Each of them has an open-drain mosfet, a weak pullup, and a lowpass filtered schmitt gate back into our FPGA. I can daisy-chain several boxes with BNC cables and tees. Each box has a 40 MHz VCXO and I want to phase-lock them, or at least time-align them to always be the same within a few microseconds, l...


High speed pulse generator to test oscilloscope

Started by Anonymous in sci.electronics.design9 years ago 12 replies

Greetings I have a Tek TDS694C I will be selling, and I'd like to demo it's high speed performance by showing it detecting a rise time - I'm...

Greetings I have a Tek TDS694C I will be selling, and I'd like to demo it's high speed performance by showing it detecting a rise time - I'm trying to remember exactly what that is - somewhere in picosecnd range? Is there a chip which will show a fast rise time? I believe they use some kind of high speed fpga? thanks in advance jb


Sigma-Delta vs. Ramp

Started by Ricketty C in sci.electronics.design2 years ago 3 replies

I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of...

I need to sample a number of analog signals in an FPGA. I don't want to use a BGA so the I/O count is rather limited as well as the variety of FPGAs. Lattice makes some nice 4kLUT parts in a 48QFN, but the I/O count tops at 39 and that has to include the JTAG/configuration signals. If I use sigma delta ADCs each one is three pins, the two pin LVDS inputs and the signal output.


DDS clock generator in LT Spice

Started by John Larkin in sci.electronics.design4 months ago 1 reply

https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0 It...

https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0 It would have been a horror to build a digital phase accumulator in LT Spice, so I did it with the bootstrapped sample-and-hold. 1 LSB is 1 volt, making a 4 kilovolt sawtooth. Close enough. We'll probably do this in a cute little efinix FPGA (digitally...


efinix bit stream question

Started by John Larkin in sci.electronics.design3 hours ago 26 replies

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic...

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic is compiled? Would a simple application use less? Are the streams very compressible? We have done some simple run-length coding to greatly reduce the storage requirement for other FPGAs. Configs tend to have long runs of 0's. The T20/256 claims...


transformer thermals

Started by Anonymous in sci.electronics.design2 years ago 54 replies

We can sense the primary current of this transformer, with a shunt and an isolated delta-sigma ADC. The FPGA squares the samples and...

We can sense the primary current of this transformer, with a shunt and an isolated delta-sigma ADC. The FPGA squares the samples and filters, so we can pick that up and square root to get RMS current. The tranny is rated for 240 VA, which would be 9.6 amps RMS in the primary. So I ran it for a few hours with 10 amps DC in the primary. Temp rise was about 26C in free air. I think people de...


Idea for a simple -1.5V 20mA power supply?

Started by Mike Randelzhofer in sci.electronics.design4 weeks ago 29 replies

As asked in the header, does anybody have an idea for simply generating a low negative voltage for indicator leds on low output voltages e.g....

As asked in the header, does anybody have an idea for simply generating a low negative voltage for indicator leds on low output voltages e.g. 0.9V on FPGA core supplies ? Non-red leds (green, yellow, white) need at least 2V or more so a direct connection to low voltage regulators for indicating presence doesn't make sense. Of course a driving NPN could be used however on many voltage...


pcb signal integrity check

Started by Anonymous in sci.electronics.design3 years ago

This is the control board of my alternator simulator. I think we are getting close to receiving a purchase...

This is the control board of my alternator simulator. I think we are getting close to receiving a purchase order! https://www.dropbox.com/s/wvyxwlwzou3thh9/T901_22.JPG?raw=1 It has high power, relay drivers, uP, FPGA, dram, ethernet, USB. It goes close to the front panel in this: https://www.dropbox.com/s/71whot11i312y63/P900_3d_3.jpg?raw=1 My homework assignment is to do the s...


FPGA as heater

Started by John Larkin in sci.electronics.design6 years ago 32 replies

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So, why not make an on-chip heater? Use a PLL to clock a bunch of flops, and vary the PLL output frequency to keep the chip temp roughly constant. -- John Larkin Highland Technology, ...


Symmetric DC-DC power transformer

Started by Anonymous in sci.electronics.design2 years ago 2 replies

I am working on a dual active bridges (4 mosfets instead of 4 diodes) by switching directions using either: 555, CPLD, FPGA or micro, depending...

I am working on a dual active bridges (4 mosfets instead of 4 diodes) by switching directions using either: 555, CPLD, FPGA or micro, depending on timing complexity. In the simplest case, just a 555 switching primary and secondary at the same time. In more complicated case, a micro switching with turn-on delay T1, turn-on time T2, turn-off delay T3 and frequency F1. What are the


DSP phase noise measurement with an SDR

Started by Andrew Holme in sci.electronics.design6 years ago 8 replies

I found this paper about measuring phase noise with just an ADC following by...

I found this paper about measuring phase noise with just an ADC following by DSP. http://jmfriedt.sequanux.org/phase_digital/grove_hein_tsc_direct_digital_PN_measurement.pdf I tried a simplified single channel experiment using an FPGA eval board: sig. gen. => ADC I = nco.cos() * ADC Q = nco.sin() * ADC I_baseband = CIC_LPF_Decimate(I) Q_baseband = CIC_LPF_Decimate(Q) angle = CORDIC


voltage drop on STRATIX FPGA supply planes

Started by coli...@yahoo.com in sci.electronics.design11 years ago 12 replies

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself,...

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself, let alone getting the power to the BGA which is dropping another 50mV. Surely the 30mV cannot be true as there is a power plane in the BGA package itself. Historically I would look at the size of the plane and assume that everything is fine and I c...


cheap ADC

Started by Anonymous in sci.electronics.design10 months ago 17 replies

This uses an FPGA LVDS input as a comparator, and one external RC, to make an ADC. Just need an algorithm to process the flop output. A...

This uses an FPGA LVDS input as a comparator, and one external RC, to make an ADC. Just need an algorithm to process the flop output. A simpler ADC should be possible. Version 4 SHEET 1 880 680 WIRE -16 0 -112 0 WIRE 48 0 -16 0 WIRE 160 0 48 0 WIRE 416 0 240 0 WIRE 480 0 416 0 WIRE 528 0 480 0 WIRE 416 48 416 0 WIRE -112 64 -112 0 WIRE 96 112 64 112 WIRE 128 112 96 112 WIRE ...