This is a DAC-programmed power supply, 48v in and 0-36 out maybe. I want to use the TI switcher, but I don't know how to wedge it into LT...

This is a DAC-programmed power supply, 48v in and 0-36 out maybe. I want to use the TI switcher, but I don't know how to wedge it into LT Spice. One of my guys can run the TI simulator, so I'll let him tune it with the TI part. We might do programmable current limiting in an FPGA, based on the current shunt measurement. Version 4 SHEET 1 1872 756 WIRE 96 -112 16 -112 WIRE 192 -112 9...

https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0 It...

https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1 https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0 It would have been a horror to build a digital phase accumulator in LT Spice, so I did it with the bootstrapped sample-and-hold. 1 LSB is 1 volt, making a 4 kilovolt sawtooth. Close enough. We'll probably do this in a cute little efinix FPGA (digitally...

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic...

We use the efinix T20 trion FPGA. Questions about the config bit streams: Are they always the same size, or does it depend on how much logic is compiled? Would a simple application use less? Are the streams very compressible? We have done some simple run-length coding to greatly reduce the storage requirement for other FPGAs. Configs tend to have long runs of 0's. The T20/256 claims...

We can sense the primary current of this transformer, with a shunt and an isolated delta-sigma ADC. The FPGA squares the samples and...

We can sense the primary current of this transformer, with a shunt and an isolated delta-sigma ADC. The FPGA squares the samples and filters, so we can pick that up and square root to get RMS current. The tranny is rated for 240 VA, which would be 9.6 amps RMS in the primary. So I ran it for a few hours with 10 amps DC in the primary. Temp rise was about 26C in free air. I think people de...

As asked in the header, does anybody have an idea for simply generating a low negative voltage for indicator leds on low output voltages e.g....

As asked in the header, does anybody have an idea for simply generating a low negative voltage for indicator leds on low output voltages e.g. 0.9V on FPGA core supplies ? Non-red leds (green, yellow, white) need at least 2V or more so a direct connection to low voltage regulators for indicating presence doesn't make sense. Of course a driving NPN could be used however on many voltage...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We...

We have a ZYNQ whose predicted timing isn't meeting decent margins. And we don't want a lot of output pin timing variation in real life. We can measure the chip temperature with the XADC thing. So, why not make an on-chip heater? Use a PLL to clock a bunch of flops, and vary the PLL output frequency to keep the chip temp roughly constant. -- John Larkin Highland Technology, ...

I found this paper about measuring phase noise with just an ADC following by...

I found this paper about measuring phase noise with just an ADC following by DSP. http://jmfriedt.sequanux.org/phase_digital/grove_hein_tsc_direct_digital_PN_measurement.pdf I tried a simplified single channel experiment using an FPGA eval board: sig. gen. => ADC I = nco.cos() * ADC Q = nco.sin() * ADC I_baseband = CIC_LPF_Decimate(I) Q_baseband = CIC_LPF_Decimate(Q) angle = CORDIC

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself,...

Guys I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power plane. It is showing a 30mV voltage drop across the BGA itself, let alone getting the power to the BGA which is dropping another 50mV. Surely the 30mV cannot be true as there is a power plane in the BGA package itself. Historically I would look at the size of the plane and assume that everything is fine and I c...

This uses an FPGA LVDS input as a comparator, and one external RC, to make an ADC. Just need an algorithm to process the flop output. A...

This uses an FPGA LVDS input as a comparator, and one external RC, to make an ADC. Just need an algorithm to process the flop output. A simpler ADC should be possible. Version 4 SHEET 1 880 680 WIRE -16 0 -112 0 WIRE 48 0 -16 0 WIRE 160 0 48 0 WIRE 416 0 240 0 WIRE 480 0 416 0 WIRE 528 0 480 0 WIRE 416 48 416 0 WIRE -112 64 -112 0 WIRE 96 112 64 112 WIRE 128 112 96 112 WIRE ...

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an...

Suppose we read in an FPGA bitstream file as 16-bit words, and want to output a compressed file, to save room in a small flash chip. If an input word is 0000, output a single 0 bit to the compressed file. If a word is nonzero, output a 1 followed by that 16-bit word. The decompressor will be very simple. I wrote a little PowerBasic program to test the compression, the input being ...