Input protection for 3.3V FPGA in a TTL world...

Started by John Robertson in sci.electronics.design2 months ago 37 replies

I am still working with a friend on a TTL level replacement for some chips on a pinball board and we have a nice FPGA (MAX 10 based) but it...

I am still working with a friend on a TTL level replacement for some chips on a pinball board and we have a nice FPGA (MAX 10 based) but it wants (of course) 3.3V I/O. I was thinking that SN74CBT16211C (24 x IO level shifter) and a TVS arrays like the D3V3X8U9LP3810-7 with a low Ohm (1 - 10R) Flame-Proof 1/8W or less resistor on the outside world interface would do for protection. ...


$/gate for MCU vs FPGA

Started by EnigmaPaul in sci.electronics.design8 years ago 8 replies

I am very curious about whether anyone would like to take a stable at calcu= lating the approximately dollar cost of a typical microcontroller of...

I am very curious about whether anyone would like to take a stable at calcu= lating the approximately dollar cost of a typical microcontroller of today = (say in the $5 to $10 range) in terms of $ per logic gate as compare that t= o the cost of a typical FPGA chip of today in a similar price range? You'll probably ask 'why would one want to do that?'. Well, I'm just curio= us and I thought...


FPGA sensitivities

Started by John Larkin in sci.electronics.design1 year ago 22 replies

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs...

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs some voltages: 1.8 aux no measurable DC effect 3.3 vccio no measurable DC effect 2.5 vccio ditto (key io's are LVDS in this bank) +1 core -10 ps per millivolt! If I vary the trigger frequency, I can see the delay heterodyning against the 1....


FPGA one-shot

Started by John Larkin in sci.electronics.design4 years ago 47 replies

I have an async signal, call it TRIG, inside a Zynq 7020. At the rising edge of TRIG, I want to make an async one-shot. It will leave the...

I have an async signal, call it TRIG, inside a Zynq 7020. At the rising edge of TRIG, I want to make an async one-shot. It will leave the chip as RX and reset some outboard ecl logic. Anything from, say, 2 ns to 10 ns width would work. The board is built, and we can't easily add more connections to the FPGA or hack in glue logic. Well, it would be ugly. Here are some ideas: https:...


What's Your Favorite Processor on an FPGA?

Started by rickman in sci.electronics.design9 years ago 82 replies

I have been working on designs of processors for FPGAs for quite a while. I have looked at the uBlaze, the picoBlaze, the NIOS, two from...

I have been working on designs of processors for FPGAs for quite a while. I have looked at the uBlaze, the picoBlaze, the NIOS, two from Lattice and any number of open source processors. Many of the open source designs were stack processors since they tend to be small and efficient in an FPGA. J1 is one I had pretty much missed until lately. It is fast and small and looks like it wa...


vector phase rotator

Started by John Larkin in sci.electronics.design8 years ago 8 replies

We did a quadrature-signal phase rotator in an FPGA, and I did this just to check my rusty high-school trig. The FPGA data is signed 16-bit...

We did a quadrature-signal phase rotator in an FPGA, and I did this just to check my rusty high-school trig. The FPGA data is signed 16-bit fractional. We digitize an incoming sine wave (called I) and delay one path through a FIFO to get 90 degree lag, which we flip to be lead (called Q) and apply the I and Q data streams to the rotator block. We get I' and Q' out, the rotated pair. ...


on-chip bypass caps

Started by John Larkin in sci.electronics.design8 years ago 58 replies

I got a spreadsheet from Altera that lists the on-chip power supply bypass caps on an Arria II GX95 FPGA. I was kind of shocked to see...

I got a spreadsheet from Altera that lists the on-chip power supply bypass caps on an Arria II GX95 FPGA. I was kind of shocked to see 32 listed capacitors, most around 1 nf, but a Vcc_core (0.9 volt) cap of 501 nF. I was told that these caps are on-chip, not in-package. Is that possible? 501 nF on an FPGA chip? -- John Larkin Highland Technology, Inc jlarkin att high...


bare-metal ZYNQ

Started by John Larkin in sci.electronics.design2 years ago 28 replies

Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot...

Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures out what the boot device is (serial flash, SD card, whatever) and reads in a secondary boot program, which the Xilinx tools provide as part of a build. That loader then reads the entire FPGA config bitstream into DRAM, and sets up a gi...


[JOB POSTING] Sought: FPGA PCB Design for Europe Electronics Company

Started by Anonymous in sci.electronics.design7 years ago

We are searching for a freelance PCB designer that is familiar with FPGA, DDR3, LVDS, SMPS, Analog-to-Digital converters, USB, PCIe, Gigabit...

We are searching for a freelance PCB designer that is familiar with FPGA, DDR3, LVDS, SMPS, Analog-to-Digital converters, USB, PCIe, Gigabit Transceivers, etc, board layout and schematic design. Has to be able to work in Altium Designer. Good learning skills are very important. Communication in written and spoken English must be very good, and has to be available online for quick re


ribbon cable TDR test

Started by John Larkin in sci.electronics.design2 years ago 20 replies

I'm going to have one board in the front of a rackmount box, the controller, with an FPGA. In the back of the box will be an output board with...

I'm going to have one board in the front of a rackmount box, the controller, with an FPGA. In the back of the box will be an output board with an ADUM7703 isolated delta-sigma converter measuring current. The boards will be connected by an 18" ribbon cable. The signals are a 20 MHz clock to the ADUM and 20 mpbs delta-sigma data coming back to the FPGA. Both sigs are source terminated. I...


big FPGA

Started by Anonymous in sci.electronics.design2 years ago 17 replies

https://www.xilinx.com/publications/product-briefs/virtex-ultrascale-plus-vu19p-product-brief.pd f Any guess what this might cost?

https://www.xilinx.com/publications/product-briefs/virtex-ultrascale-plus-vu19p-product-brief.pd f Any guess what this might cost?


FIR chips

Started by Syd Rumpo in sci.electronics.design10 years ago 25 replies

Does anyone make FIR filter chips? Harris used to decades ago. I need 16 bits, 128 taps and 30MHz. FPGA of course, but I'd like lower...

Does anyone make FIR filter chips? Harris used to decades ago. I need 16 bits, 128 taps and 30MHz. FPGA of course, but I'd like lower power. Cheers -- Syd


placing a board

Started by Anonymous in sci.electronics.design2 years ago 10 replies

https://www.dropbox.com/s/gm0awkc0489s6om/T901_15.JPG?raw=1 I'm doing the placement on this one. I have the circuit in my head, and I know...

https://www.dropbox.com/s/gm0awkc0489s6om/T901_15.JPG?raw=1 I'm doing the placement on this one. I have the circuit in my head, and I know about the many electrical constraints, so it's easier to do the critical stuff myself, instead of trying to explain it all to my layout people. The issue now is, can this be done in 6 layers? Probably not, but only the FPGA-DDR3 bit really needs ...


Enclustra business model

Started by Piotr Wyderski in sci.electronics.design4 years ago 7 replies

The schematics of their Zynq modules is not publicly available and they have just refused to send me a copy because it is only available to get...

The schematics of their Zynq modules is not publicly available and they have just refused to send me a copy because it is only available to get them after the purchase. How could I know if I want to purachase their modules at all if there is no way to check how is the RTC connected to the FPGA chip or how many analog inputs are available? What happened to those guys? Best regards, Piot...


Altera FPGA pseudoinstruction, RAM configuration

Started by Bruce Varley in sci.electronics.design9 years ago 1 reply

Does anyone know the Verilog command within the Altera Quartus II IDE for forcing 2-d boolean arrays to be implemented using internal RAM...

Does anyone know the Verilog command within the Altera Quartus II IDE for forcing 2-d boolean arrays to be implemented using internal RAM hardware, rather than as linked logic elements?


WTF Xilinx...

Started by Fred Bartoli in sci.electronics.design9 years ago 3 replies

For a customer I have to install some xilinx SW to flash an FPGA design of theirs. D/L their last release of labtools... 1.1Go, no...

For a customer I have to install some xilinx SW to flash an FPGA design of theirs. D/L their last release of labtools... 1.1Go, no less. Well, I expect be able to select the programming tool I want, so lets go for the install. Crap, it barfs 4Go on my HD. Morons... -- Thanks, Fred.


QDR ii+ Simulations on Hyperlynx

Started by Anonymous in sci.electronics.design5 years ago

Hi, I'm using Hyperlynx to simulate QDR II+ connected to my Kintex FPGA. I'm using DDRx wizard in hyperlynx for that. Still I couldn't find...

Hi, I'm using Hyperlynx to simulate QDR II+ connected to my Kintex FPGA. I'm using DDRx wizard in hyperlynx for that. Still I couldn't find any proper documentation for QDR II+. Can anyone help me? Regards, Sanjeewa


Strong low-pass filter

Started by pw in sci.electronics.design9 years ago 48 replies

I want to make a low-pass filter (-0.1 dB/20kHz, -150dB/22050Hz) for digital audio 44.1...192kHz (from S/PDIF). What use for this ? DSP...

I want to make a low-pass filter (-0.1 dB/20kHz, -150dB/22050Hz) for digital audio 44.1...192kHz (from S/PDIF). What use for this ? DSP processor OR FPGA OR something other? What is the easiest way to do this? Thanks in advance Pawel


MicroZED

Started by John Larkin in sci.electronics.design8 years ago 119 replies

Has anybody used the MicroZED? It looks like a good subassembly to use on a controller board. The documentation, especially on...

Has anybody used the MicroZED? It looks like a good subassembly to use on a controller board. The documentation, especially on mechanicals, is spotty. We have an upcoming project that needs a uP, FPGA, Ethernet, DRAM, all that stuff. It's tempting to buy a little board that has all that done and working, running Linux out of the box. -- John Larkin Highland Technology...


fast edges

Started by Gerhard Hoffmann in sci.electronics.design9 years ago 19 replies

from usenet: On Sat, 9 Feb 2013 10:42:12 -0800 (PST), radams2000@gmail.com wrote: > A these speeds you are mostly talking about integrated...

from usenet: On Sat, 9 Feb 2013 10:42:12 -0800 (PST), radams2000@gmail.com wrote: > A these speeds you are mostly talking about integrated versus discrete circuits. Do any of the most recent fpga's meet your needs? They are in 28nm which is blazingly fast but I'm not sure if the i/o would keep up > > Bob I'm after the fastest possible pulses to drive an electro-optic modulato