555 timer

Started by George Herold in sci.electronics.design10 years ago 41 replies

Hey, I think I=92ve got a use for a few dual 555 timers. (First time in ~20 years) I want to make some signal sources with a max freq. of maybe...

Hey, I think I=92ve got a use for a few dual 555 timers. (First time in ~20 years) I want to make some signal sources with a max freq. of maybe 100kHz. (I figure I=92ll heavily RC filter the output) I was going to order the CMOS version (TS556). Is there any reason to use the TTL one? (NE556) The minuscule cost difference makes no difference to me. Thanks, George H.


semiconductor drift

Started by John Larkin in sci.electronics.design7 years ago 52 replies

We have two 8-channel waveform generators that were shipped 4 months ago, and came back because the customer ordered too many or something. We...

We have two 8-channel waveform generators that were shipped 4 months ago, and came back because the customer ordered too many or something. We routinely test anything that comes back, before returning them or returning to stock. What's interesting is that all 16 channels have a negative DC offset. Each channel is a diff-current-output cmos DAC, an opamp diffamp, a passive LC filter, and ...


night vision toy

Started by John Larkin in sci.electronics.design5 years ago 8 replies

https://www.amazon.com/gp/product/B00THZ2NFE/ref=oh_aui_detailpage_o03_s00?ie=UTF8&psc=1 This is pretty neat. It's some sort of CCD or...

https://www.amazon.com/gp/product/B00THZ2NFE/ref=oh_aui_detailpage_o03_s00?ie=UTF8&psc=1 This is pretty neat. It's some sort of CCD or CMOS color imager. It's not as sensitive as a Gen1 tube, but it's pretty good. It seems to be very sensitive to near IR at 850 nm, and also to my UV flashlight, 395 nm. Gotta try some more wavelengths. At its lowest illuminator setting, it lights u...


Weird EMC circuit

Started by Tim Williams in sci.electronics.design7 years ago 5 replies

I'm doing some EMC work right now, and created something weird. Has anyone seen it before? Description: Suppose you have a shielded cable...

I'm doing some EMC work right now, and created something weird. Has anyone seen it before? Description: Suppose you have a shielded cable being terminated to a header. So, you tie the shield to a pin, and ground that on the board. The rest of the wires are signal, power, ground, that sort of thing. For purposes of example, say it's CMOS logic level (impedance controlled for signa...


74LS47 substitution

Started by bitrex in sci.electronics.design5 years ago 23 replies

Is there a CMOS-type substitute for the 74LS47 with "open collector" type outputs suitable for sinking around 20mA? That uses less quiescent...

Is there a CMOS-type substitute for the 74LS47 with "open collector" type outputs suitable for sinking around 20mA? That uses less quiescent power than the 47's ~10mA. Supply voltage either 5 or 3.3 volts, depending. It doesn't really matter if the chip itself does a conversion from BCD to the appropriate outputs, as that mapping can be done in software, but the chip would need to have ...


Killed one of the new 3 dollar 40 cent multimters

Started by Jan Panteltje in sci.electronics.design10 years ago 16 replies

Killed one of the new 3 dollar 40 cent multimeters OK, they are only 1 kV, and I went to 1900 V and higher. So this is the third dead...

Killed one of the new 3 dollar 40 cent multimeters OK, they are only 1 kV, and I went to 1900 V and higher. So this is the third dead multimeter, it shows very erratic readings now on all ranges, chip CMOS isolation pierced I think, actually it may have seen as much as 2700 V and that while changing voltage ranges. So, anyways, I have some nice analog 100 uA (IIRC) huge meters somewhere ...


building an electromagnetic pulser for pain relief. Know which issue this was?

Started by ausrpned in sci.electronics.design4 years ago 6 replies

Have been looking for a copy of the article in an early issue of Elektor sold in Australia. From memory a single CMOS chip was used, the output...

Have been looking for a copy of the article in an early issue of Elektor sold in Australia. From memory a single CMOS chip was used, the output was to a wire wound bolt from memory. Powered by a 9V battery. Any one have a copy or know which issue published the article? Cheers --


Low Jitter 20MHz oscillator

Started by hbv in sci.electronics.design9 years ago 49 replies

Hi all, We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single ended ), 20Mhz (+-few percent...) and most important a low...

Hi all, We need a low jitter clock generator ( 3v3 or 1v8 CMOS output single ended ), 20Mhz (+-few percent...) and most important a low jitter on this output (few ps). Any ideas are welcomed. Habib.


7-segment LCD to BCD decoder ?

Started by N_Cook in sci.electronics.design7 years ago 83 replies

Assuming one back-plane to consider , what would be most efficient component-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to...

Assuming one back-plane to consider , what would be most efficient component-count/least complex discrete/CMOS/74 route , ie not pic/Pi/uC to firstly convert the ex-oring business to proper levels and then the "mapping", output could be linear per digit rather than bcd. Starting with an off-the-shelf commercial unit where the LCD display is driven off a uC, to give a remotely monitorable ...


Making secure mechanical connection to IC pins to modify equipment

Started by bitrex in sci.electronics.design5 years ago 6 replies

I have a piece of music gear on my bench which I'm modding for a client. Needs some new wires attached to the uP bus to fan out to some CMOS...

I have a piece of music gear on my bench which I'm modding for a client. Needs some new wires attached to the uP bus to fan out to some CMOS logic on a daughterboard. What's the the neatest way to secure these new connections? Soldering the wires to the pins on the underside of the PCB is one option, but doesn't seem very mechanically secure, or professional.


complementary cmos levels

Started by Anonymous in sci.electronics.design2 years ago 11 replies

I have a fast 3.3 volt logic level that I'd like to split into inverted and non-inverted copies with minimum time skew. I think that TI...

I have a fast 3.3 volt logic level that I'd like to split into inverted and non-inverted copies with minimum time skew. I think that TI once had a buffer with one input and complementary outputs, but I can't find a reference to that. It's probably slow and obsolete. A TTL to RS485 converter sort of works but would be slow. I could use two separate XOR gates, one as a buffer and the...


Mixed-signal model of CD4093

Started by bitrex in sci.electronics.design4 years ago 6 replies

Is there a mixed-signal model of the CD4093 NAND Schmitt available that can be used in LTSpice? One that includes power supply connections and...

Is there a mixed-signal model of the CD4093 NAND Schmitt available that can be used in LTSpice? One that includes power supply connections and shows realistic supply currents, etc. Or any of that fashion of CMOS family such as hex inverters that can also be used as negative-feedback analog amplifiers


OT: Can CMOS battery on PC motherboard be hot-swapped?

Started by Joerg in sci.electronics.design9 years ago 74 replies

Folks, Got a Dell Vostro 200 mini tower with XP on there that seems to be a bit off in the realtime clock lately. Around five years old so...

Folks, Got a Dell Vostro 200 mini tower with XP on there that seems to be a bit off in the realtime clock lately. Around five years old so needs a new 3V coin cell on the mobo. In order not to lose all the setup stuff, can those CR2032 coin cells be hot-swapped while the PC is running? Of course using ESD straps, being careful and all that. -- Regards, Joerg http://www.analogco...


SMT-on-copper-clad

Started by bitrex in sci.electronics.design2 years ago 4 replies

Using "surfboards" to mount about a half-dozen SMT cmos logic to a copper clad, how many by-pass/de-glitcher caps do you put on and where do...

Using "surfboards" to mount about a half-dozen SMT cmos logic to a copper clad, how many by-pass/de-glitcher caps do you put on and where do you put them when you use this "style"? frequencies in the 10s of MHz. Do you put one on each chip (seems like overkill) or do you bypass at the power input and rely on distributed capacitance of the board?


e-phemts as logic gates

Started by John Larkin in sci.electronics.design3 years ago 3 replies

https://www.dropbox.com/s/yhi1s5yw983prw3/Phemt_Gates.JPG?dl=0 There are only a couple of 1-ns-class cmos Tiny Logic gates, an AND and a...

https://www.dropbox.com/s/yhi1s5yw983prw3/Phemt_Gates.JPG?dl=0 There are only a couple of 1-ns-class cmos Tiny Logic gates, an AND and a DFF. Everything else is slow. These SAV-551 Mini-Circuits ephmets are only about $1 each, and they can make crazy fast NAND and NOR gates. Rds-on is a few ohms and capacitances are small. Output falling edges are faster than rising, but that suits my...


Can someone retrieve this IEEE paper for me?

Started by Jim Thompson in sci.electronics.design9 years ago 16 replies

Can someone retrieve this IEEE paper for me? Fiori, F.; Crovetti, P.S, "A new compact temperature-compensated CMOS current reference,"...

Can someone retrieve this IEEE paper for me? Fiori, F.; Crovetti, P.S, "A new compact temperature-compensated CMOS current reference," Circuits and Systems II: Express Briefs, IEEE Transactions on ,2005, vol.52, no.11, pp. 724- 728. Thanks! ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovat...


Possible PLL Lock Indicator?

Started by Jim Thompson in sci.electronics.design4 years ago 40 replies

Possible PLL Lock Indicator? (Assuming PFD) TD varied from 9.9ns to 10.1ns in 0.5ps Steps. Where you place the delay (inverters)...

Possible PLL Lock Indicator? (Assuming PFD) TD varied from 9.9ns to 10.1ns in 0.5ps Steps. Where you place the delay (inverters) would depend on if set-up-and-hold time of D-Flop's are positive or negative. Logic is _real_ 0.18um CMOS. ...Jim Thompson --


integrated circuit modeling with LTSpice

Started by Michael Robinson in sci.electronics.design10 years ago 14 replies

I'm in the unfortunate position of having to use LTSpice to work on a CMOS circuit design. If you must know why, our school's Cadence...

I'm in the unfortunate position of having to use LTSpice to work on a CMOS circuit design. If you must know why, our school's Cadence installation has bugs. So far I've figured out I can make a level 1 model that successfully shows body effect. I'm working on the parasitics. I can put in a values for Cbd and Cbs; to get Cgs and Cgd I have to put in Cgso Cgdo and specify the gate dime...


LDO's for Dummies

Started by Jim Thompson in sci.electronics.design10 years ago 7 replies

http://www.analog-innovations.com/SED/LDOs_for_Dummies_Simple_LDO_NMOS+4_Bipolar_Transistors.pdf Shown with 10mA pre-load, 100mA transient...

http://www.analog-innovations.com/SED/LDOs_for_Dummies_Simple_LDO_NMOS+4_Bipolar_Transistors.pdf Shown with 10mA pre-load, 100mA transient load. Drops to 1.15V with 1A transient. Thank You, Thank You, John "Tourette's by keyboard" Larkin, exemplary of Tulane graduates... I'll get a patent out of that one (for the CMOS version, bipolar shown). Jason Betts and Ian Field should be so pr


24V Gate Driver, cheap

Started by Klaus Kragelund in sci.electronics.design6 years ago 30 replies

Hey I need a CMOS gate to drive high side N channel MOSFETs. Power rail is 24VDC First idea is the CD4050, but it's 0.1...

Hey I need a CMOS gate to drive high side N channel MOSFETs. Power rail is 24VDC First idea is the CD4050, but it's 0.1 USD https://www.fairchildsemi.com/datasheets/cd/cd4049ubc.pdf Is there any device that comes close to that price and has better drive current? Or perhaps a buffer, than can run from 30VDC, then I can throw away the level shifting also (driven from 5V logic)? Che...