Digital PLL's -- Part 2
In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter. Now let’s look at this PLL in the Z-domain [1, 2]. We will find that the response is characterized by a loop natural...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Introduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
Digital PLL's -- Part 1
1. Introduction Figure 1.1 is a block diagram of a digital PLL (DPLL). The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal. The loop includes a phase detector to compute ...
Stability or insanity
I've just spent over two weeks getting ready to do my next video. It was a combination of one of those vast underestimations one occasionally makes, combined with falling into a bit of an obsession.I am, at this point, not only wondering if...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Introduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
Digital PLL's -- Part 2
In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter. Now let’s look at this PLL in the Z-domain [1, 2]. We will find that the response is characterized by a loop natural...
Digital PLL's -- Part 1
1. Introduction Figure 1.1 is a block diagram of a digital PLL (DPLL). The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal. The loop includes a phase detector to compute ...
Stability or insanity
I've just spent over two weeks getting ready to do my next video. It was a combination of one of those vast underestimations one occasionally makes, combined with falling into a bit of an obsession.I am, at this point, not only wondering if...
Digital PLL's -- Part 2
In Part 1, we found the time response of a 2nd order PLL with a proportional + integral (lead-lag) loop filter. Now let’s look at this PLL in the Z-domain [1, 2]. We will find that the response is characterized by a loop natural...
Use DPLL to Lock Digital Oscillator to 1PPS Signal
Introduction There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency...
Digital PLL's -- Part 1
1. Introduction Figure 1.1 is a block diagram of a digital PLL (DPLL). The purpose of the DPLL is to lock the phase of a numerically controlled oscillator (NCO) to a reference signal. The loop includes a phase detector to compute ...
Stability or insanity
I've just spent over two weeks getting ready to do my next video. It was a combination of one of those vast underestimations one occasionally makes, combined with falling into a bit of an obsession.I am, at this point, not only wondering if...
