I want to tap into the power of a circa 1980 digital board to power my
own board.  My question is whether the 5V coming from this old board
is clean enough to use directly or if I should add my own power
management circuitry.

The device is powered from 120Vac, goes through a transformer to step
down to 10Vac, goes through a bridge rectifier, then enters an
LM340-5.  Is this 5V output clean enough for use with an Atmel AVR?
Were parts on the older board (old NMOS parts such as the MOS 6522)
more tolerant of noisy supplies?

Pete

> I want to tap into the power of a circa 1980 digital board to power my
> own board.  My question is whether the 5V coming from this old board
> is clean enough to use directly or if I should add my own power
> management circuitry.
> 
> The device is powered from 120Vac, goes through a transformer to step
> down to 10Vac, goes through a bridge rectifier, then enters an
> LM340-5.  Is this 5V output clean enough for use with an Atmel AVR?
> Were parts on the older board (old NMOS parts such as the MOS 6522)
> more tolerant of noisy supplies?

Noise margin of CMOS has remained the same since its inception. There 
will be no problem. Just be sure to put a power entry capacitor on your 
Atmel board right at the 5V/GND wire attachment point of 1uF or 10x the 
combined decoupling capacitance in your circuit, whichever is larger...

On Apr 7, 10:47=A0am, Fred Bloggs <nos...@nospam.com> wrote:
> Noise margin of CMOS has remained the same since its inception. There
> will be no problem. Just be sure to put a power entry capacitor on your
> Atmel board right at the 5V/GND wire attachment point of 1uF or 10x the
> combined decoupling capacitance in your circuit, whichever is larger...

A couple of questions.

1.  The older board is NMOS, not CMOS.  Is this difference
significant?
2.  Noise margin is a function of I/O (Voh an Vol).  I'm not sure how
this relates to a noisy power supply.  Can you clarify?

Pete

Suudy wrote:
> On Apr 7, 10:47 am, Fred Bloggs <nos...@nospam.com> wrote:
> 
>>Noise margin of CMOS has remained the same since its inception. There
>>will be no problem. Just be sure to put a power entry capacitor on your
>>Atmel board right at the 5V/GND wire attachment point of 1uF or 10x the
>>combined decoupling capacitance in your circuit, whichever is larger...
> 
> 
> A couple of questions.
> 
> 1.  The older board is NMOS, not CMOS.  Is this difference
> significant?

NMOS predates me so I don't know much about it, but see below...

> 2.  Noise margin is a function of I/O (Voh an Vol).  I'm not sure how
> this relates to a noisy power supply.  Can you clarify?

CMOS noise margin is huge, typically a full 1/3 of power supply, which 
is 1.7V for a 5V system. A real bad supply is maybe 100mV noise, the 
CMOS will not even see it. CMOS is the safest and most noise immune 
logic family in existence. It would VERY unusual for the old power 
supply to cause problems. You could measure the noise with a scope 
instead of asking hypothetical questions...

On Apr 7, 11:11=A0am, Fred Bloggs <nos...@nospam.com> wrote:
> CMOS noise margin is huge, typically a full 1/3 of power supply, which
> is 1.7V for a 5V system. A real bad supply is maybe 100mV noise, the
> CMOS will not even see it. CMOS is the safest and most noise immune
> logic family in existence. It would VERY unusual for the old power

I still don't see how a noisy power supply relates to noise margin.
Assuming 5V I/O, I can see how noise can appear on the outputs, and
the large noise margin is useful.  But internally to the parts, I'm
not so sure how tolerant they are to a noisy supply.  That is where I
was going.  What about internal PLL's (such as for USB)?  This is my
confusion.

The datasheets, such as for the AT90USB64/128 make no mention of power
cleanliness.  Is there some unwritten rule of thumb that everyone
uses?

> supply to cause problems. You could measure the noise with a scope
> instead of asking hypothetical questions...

If I had a few grand laying around that my wife would let me spend on
a scope, I could do that.  But even if I did measure it, it would not
answer the question of how clean it needs to be.  What is tolerable?
Tens of mV of ripple?  Hundreds?

Pete

Suudy <p...@mudplace.org> wrote:
>I want to tap into the power of a circa 1980 digital board to power my
>own board.  My question is whether the 5V coming from this old board
>is clean enough to use directly or if I should add my own power
>management circuitry.

You may want to check the capacitors due the age.

Suudy wrote:

> What about internal PLL's (such as for USB)?

That wasn't what you originally asked ! It might in some cases be worth
adding additional filtering on the supply going to such parts.


> The datasheets, such as for the AT90USB64/128 make no mention of power
> cleanliness.  Is there some unwritten rule of thumb that everyone
> uses?

No real need typically.


> > supply to cause problems. You could measure the noise with a scope
> > instead of asking hypothetical questions...
>
> If I had a few grand laying around that my wife would let me spend on
> a scope, I could do that.

A cheap secondhand scope will measure some noise just fine.

Graham

s...@trline4.org wrote:

> Suudy <p...@mudplace.org> wrote:
> >I want to tap into the power of a circa 1980 digital board to power my
> >own board.  My question is whether the 5V coming from this old board
> >is clean enough to use directly or if I should add my own power
> >management circuitry.
>
> You may want to check the capacitors due the age.

As in electrolytic capacitors. They do age ( lose value and suffer
increased ESR).

Graham

On Mon, 7 Apr 2008 11:58:44 -0700 (PDT), Suudy <p...@mudplace.org>
wrote:

>On Apr 7, 11:11 am, Fred Bloggs <nos...@nospam.com> wrote:
>> CMOS noise margin is huge, typically a full 1/3 of power supply, which
>> is 1.7V for a 5V system. A real bad supply is maybe 100mV noise, the
>> CMOS will not even see it. CMOS is the safest and most noise immune
>> logic family in existence. It would VERY unusual for the old power
>
>I still don't see how a noisy power supply relates to noise margin.

---
http://www.interfacebus.com/Logic_Family_Noise_Margin.html

JF

On Apr 7, 1:13 pm, Eeyore <rabbitsfriendsandrelati...@hotmail.com>
wrote:
> Suudy wrote:
> > What about internal PLL's (such as for USB)?
>
> That wasn't what you originally asked ! It might in some cases be worth
> adding additional filtering on the supply going to such parts.

Sorry, I was trying to be generic.  I figured with the small
geometries used (I don't know what process Atmel uses, but it probably
is smaller than the old 2u days), that power supply noise would be a
much bigger issue nowadays.  And with the advanced peripheral options
and internal PLLs, noise seems even more of an issue.

> > The datasheets, such as for the AT90USB64/128 make no mention of power
> > cleanliness.  Is there some unwritten rule of thumb that everyone
> > uses?
>
> No real need typically.

So if they don't specifically mention it, than as long as the noise
doesn't cause the noise margins to go to hell, it is probably fine
then?

> > > supply to cause problems. You could measure the noise with a scope
> > > instead of asking hypothetical questions...
>
> > If I had a few grand laying around that my wife would let me spend on
> > a scope, I could do that.
>
> A cheap secondhand scope will measure some noise just fine.

"Cheap" is relative.  More than about $50, and I get an earful.  My
wife is a bigger penny pincher than my boss.  Seems I have to budget
my homebrew projects farther in advance with her than with my boss.

Perhaps I'll bring in the device to work and do a quick measurement.

On Apr 7, 2:39=A0pm, John Fields <jfie...@austininstruments.com> wrote:
> >I still don't see how a noisy power supply relates to noise margin.
>
> ---http://www.interfacebus.com/Logic_Family_Noise_Margin.html

Thanks for the link.  I wasn't aware that noise on the power supply
could propogate that much into the I/O.  Granted, the output drivers
are powered, but I figured with bypass caps and internal capacitance,
it wouldn't have that much of an effect.