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design | 24Hz to 60Hz PLL?
There are 63 messages in this thread.
You are currently looking at messages 30 to 40.
Re: 24Hz to 60Hz PLL? - John Larkin - 2010-02-13 17:16:00
On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <w...@gmail.com> wrote: >On Feb 12, 2:44 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >> >> <christopher.man...@gmail.com> wrote: >> >I need to make a PLL that slaves to a 24Hz square wave. The output of >> >the loop would be a 60Hz square wave. > >> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >> and lock at 12 Hz. > >Right chip, but the best strategy is to lock a high frequency to a >multiple >of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >the highest frequency, and the noise pickup would improve if >you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >and by five then by two to get the 24 Hz for the phase comparison. > >The 'divide by two' on each branch guarantees accurate 50% duty cycle, >many >counters have asymmetric outputs. The input only furnishes information 24 times a second (48 if you can use both edges) so it doesn't much matter what the oscillator frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be any better. Granted, 24 is twice as good as 12. So you could run the VCO at 120, and then divide by 5 to get 24 for the pll, and also divide by 2 to get the 60. The phase:frequency detector in the 4046 is edge sensitive, so duty cycle doesn't matter if you use that one. John
Re: 24Hz to 60Hz PLL? - Jim Thompson - 2010-02-13 17:39:00
On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin <j...@highNOTlandTHIStechnologyPART.com> wrote: >On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <w...@gmail.com> >wrote: > >>On Feb 12, 2:44 pm, John Larkin >><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>> >>> <christopher.man...@gmail.com> wrote: >>> >I need to make a PLL that slaves to a 24Hz square wave. The output of >>> >the loop would be a 60Hz square wave. >> >>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>> and lock at 12 Hz. >> >>Right chip, but the best strategy is to lock a high frequency to a >>multiple >>of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>the highest frequency, and the noise pickup would improve if >>you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>and by five then by two to get the 24 Hz for the phase comparison. >> >>The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>many >>counters have asymmetric outputs. > >The input only furnishes information 24 times a second (48 if you can >use both edges) so it doesn't much matter what the oscillator >frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >any better. > >Granted, 24 is twice as good as 12. So you could run the VCO at 120, >and then divide by 5 to get 24 for the pll, and also divide by 2 to >get the 60. > >The phase:frequency detector in the 4046 is edge sensitive, so duty >cycle doesn't matter if you use that one. > >John John's last paragraph is absolutely correct... Ron Treadway and I designed it to be that way :-P ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Re: 24Hz to 60Hz PLL? - BobW - 2010-02-13 17:54:00
"Jim Thompson" <T...@My-Web-Site.com> wrote in message news:o...@4ax.com... > On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin > <j...@highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <w...@gmail.com> >>wrote: >> >>>On Feb 12, 2:44 pm, John Larkin >>><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>> >>>> <christopher.man...@gmail.com> wrote: >>>> >I need to make a PLL that slaves to a 24Hz square wave. The output of >>>> >the loop would be a 60Hz square wave. >>> >>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>> and lock at 12 Hz. >>> >>>Right chip, but the best strategy is to lock a high frequency to a >>>multiple >>>of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>>the highest frequency, and the noise pickup would improve if >>>you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>>and by five then by two to get the 24 Hz for the phase comparison. >>> >>>The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>>many >>>counters have asymmetric outputs. >> >>The input only furnishes information 24 times a second (48 if you can >>use both edges) so it doesn't much matter what the oscillator >>frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >>any better. >> >>Granted, 24 is twice as good as 12. So you could run the VCO at 120, >>and then divide by 5 to get 24 for the pll, and also divide by 2 to >>get the 60. >> >>The phase:frequency detector in the 4046 is edge sensitive, so duty >>cycle doesn't matter if you use that one. >> >>John > > John's last paragraph is absolutely correct... Ron Treadway and I > designed it to be that way :-P > > ...Jim Thompson Really? I loved the 4046 and used it in several designs. Bob -- == All google group posts are automatically deleted due to spam ==
Re: 24Hz to 60Hz PLL? - Jim Thompson - 2010-02-13 18:24:00
On Sat, 13 Feb 2010 14:54:00 -0800, "BobW" <n...@roadrunner.com> wrote: > >"Jim Thompson" <T...@My-Web-Site.com> wrote in >message news:o...@4ax.com... >> On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin >> <j...@highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd <w...@gmail.com> >>>wrote: >>> >>>>On Feb 12, 2:44 pm, John Larkin >>>><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>>> >>>>> <christopher.man...@gmail.com> wrote: >>>>> >I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>> >the loop would be a 60Hz square wave. >>>> >>>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>>> and lock at 12 Hz. >>>> >>>>Right chip, but the best strategy is to lock a high frequency to a >>>>multiple >>>>of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>>>the highest frequency, and the noise pickup would improve if >>>>you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>>>and by five then by two to get the 24 Hz for the phase comparison. >>>> >>>>The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>>>many >>>>counters have asymmetric outputs. >>> >>>The input only furnishes information 24 times a second (48 if you can >>>use both edges) so it doesn't much matter what the oscillator >>>frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >>>any better. >>> >>>Granted, 24 is twice as good as 12. So you could run the VCO at 120, >>>and then divide by 5 to get 24 for the pll, and also divide by 2 to >>>get the 60. >>> >>>The phase:frequency detector in the 4046 is edge sensitive, so duty >>>cycle doesn't matter if you use that one. >>> >>>John >> >> John's last paragraph is absolutely correct... Ron Treadway and I >> designed it to be that way :-P >> >> ...Jim Thompson > >Really? > >I loved the 4046 and used it in several designs. > >Bob The 4046 is actually a CMOS translation and copy, merging my MC4024 VCM and Ron's and my MC4044 PFD, both done originally in TTL (around 1968). The MC4024 was good up to around 30MHz (it was really PECL with a translator to TTL ;-) Later there were actual PECL releases: MC1658 VCM, and MC12040 PFD. Then there's also my MC1648 tank-type VCO... no longer made :-( Though I designed an improved replica on a custom ASIC just this last year. One of my original OpAmps, the MC1530/31, designed in 1963, is still being manufactured (by Lansdale)... made for 47 years now ;-) ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Re: 24Hz to 60Hz PLL? - Phil Hobbs - 2010-02-13 20:36:00
On 2/13/2010 5:39 PM, Jim Thompson wrote: > On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin > <j...@highNOTlandTHIStechnologyPART.com> wrote: > >> On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd<w...@gmail.com> >> wrote: >> >>> On Feb 12, 2:44 pm, John Larkin >>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>> >>>> <christopher.man...@gmail.com> wrote: >>>>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>> the loop would be a 60Hz square wave. >>> >>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>> and lock at 12 Hz. >>> >>> Right chip, but the best strategy is to lock a high frequency to a >>> multiple >>> of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>> the highest frequency, and the noise pickup would improve if >>> you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>> and by five then by two to get the 24 Hz for the phase comparison. >>> >>> The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>> many >>> counters have asymmetric outputs. >> >> The input only furnishes information 24 times a second (48 if you can >> use both edges) so it doesn't much matter what the oscillator >> frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >> any better. >> >> Granted, 24 is twice as good as 12. So you could run the VCO at 120, >> and then divide by 5 to get 24 for the pll, and also divide by 2 to >> get the 60. >> >> The phase:frequency detector in the 4046 is edge sensitive, so duty >> cycle doesn't matter if you use that one. >> >> John > > John's last paragraph is absolutely correct... Ron Treadway and I > designed it to be that way :-P > > ...Jim Thompson So how come you put that stupid deadband in there? ;) Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
Re: 24Hz to 60Hz PLL? - Jim Thompson - 2010-02-13 21:08:00
On Sat, 13 Feb 2010 20:36:35 -0500, Phil Hobbs <p...@electrooptical.net> wrote: >On 2/13/2010 5:39 PM, Jim Thompson wrote: >> On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin >> <j...@highNOTlandTHIStechnologyPART.com> wrote: >> >>> On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd<w...@gmail.com> >>> wrote: >>> >>>> On Feb 12, 2:44 pm, John Larkin >>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>>> >>>>> <christopher.man...@gmail.com> wrote: >>>>>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>>> the loop would be a 60Hz square wave. >>>> >>>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>>> and lock at 12 Hz. >>>> >>>> Right chip, but the best strategy is to lock a high frequency to a >>>> multiple >>>> of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>>> the highest frequency, and the noise pickup would improve if >>>> you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>>> and by five then by two to get the 24 Hz for the phase comparison. >>>> >>>> The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>>> many >>>> counters have asymmetric outputs. >>> >>> The input only furnishes information 24 times a second (48 if you can >>> use both edges) so it doesn't much matter what the oscillator >>> frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >>> any better. >>> >>> Granted, 24 is twice as good as 12. So you could run the VCO at 120, >>> and then divide by 5 to get 24 for the pll, and also divide by 2 to >>> get the 60. >>> >>> The phase:frequency detector in the 4046 is edge sensitive, so duty >>> cycle doesn't matter if you use that one. >>> >>> John >> >> John's last paragraph is absolutely correct... Ron Treadway and I >> designed it to be that way :-P >> >> ...Jim Thompson > >So how come you put that stupid deadband in there? ;) > >Cheers > >Phil Hobbs That's a mismatched delay issue. Later versions have that "fixed" by overlapping the U/D outputs. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Re: 24Hz to 60Hz PLL? - Phil Hobbs - 2010-02-13 22:14:00
On 2/13/2010 9:08 PM, Jim Thompson wrote: > On Sat, 13 Feb 2010 20:36:35 -0500, Phil Hobbs > <p...@electrooptical.net> wrote: > >> On 2/13/2010 5:39 PM, Jim Thompson wrote: >>> On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin >>> <j...@highNOTlandTHIStechnologyPART.com> wrote: >>> >>>> On Sat, 13 Feb 2010 12:53:07 -0800 (PST), whit3rd<w...@gmail.com> >>>> wrote: >>>> >>>>> On Feb 12, 2:44 pm, John Larkin >>>>> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>>>> On Fri, 12 Feb 2010 14:14:04 -0800 (PST), Chris >>>>>> >>>>>> <christopher.man...@gmail.com> wrote: >>>>>>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>>>> the loop would be a 60Hz square wave. >>>>> >>>>>> CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five >>>>>> and lock at 12 Hz. >>>>> >>>>> Right chip, but the best strategy is to lock a high frequency to a >>>>> multiple >>>>> of the 24 Hz, NOT to lock at 12 Hz. The loop filter works better at >>>>> the highest frequency, and the noise pickup would improve if >>>>> you went higher than that. Then, divide 240 by 4 to get the 60 Hz, >>>>> and by five then by two to get the 24 Hz for the phase comparison. >>>>> >>>>> The 'divide by two' on each branch guarantees accurate 50% duty cycle, >>>>> many >>>>> counters have asymmetric outputs. >>>> >>>> The input only furnishes information 24 times a second (48 if you can >>>> use both edges) so it doesn't much matter what the oscillator >>>> frequency is. The VCO could be 60KHz and the loop dynamics wouldn't be >>>> any better. >>>> >>>> Granted, 24 is twice as good as 12. So you could run the VCO at 120, >>>> and then divide by 5 to get 24 for the pll, and also divide by 2 to >>>> get the 60. >>>> >>>> The phase:frequency detector in the 4046 is edge sensitive, so duty >>>> cycle doesn't matter if you use that one. >>>> >>>> John >>> >>> John's last paragraph is absolutely correct... Ron Treadway and I >>> designed it to be that way :-P >>> >>> ...Jim Thompson >> >> So how come you put that stupid deadband in there? ;) >> >> Cheers >> >> Phil Hobbs > > That's a mismatched delay issue. Later versions have that "fixed" by > overlapping the U/D outputs. > > ...Jim Thompson Sort of hard to fix when the pulse goes completely away--with a given slew rate, there's some range in which both the height and width of the pulse depend on the phase error--which produces a flat spot in the V(phi) curve. Or do the fixed versions pulse high, pulse low, and then go tri-state at zero phase error? That would still give some ripple, but that's a big improvement over deadbands. Any part numbers with the fixed version? That caused me grief as a youth, till I realized I could just use a resistor to ground to move the set point a bit away from phi=0. Thanks Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
Re: 24Hz to 60Hz PLL? - Robert Baer - 2010-02-14 05:43:00
Jim Thompson wrote: > On Sat, 13 Feb 2010 16:37:53 +0100, Fred Bartoli <" "> wrote: > >> Chris a écrit : >>> On Feb 12, 3:21 pm, Fred Bartoli <" "> wrote: >>>> Chris a écrit : >>>> >>>>> I need to make a PLL that slaves to a 24Hz square wave. The output of >>>>> the loop would be a 60Hz square wave. Any CMOS level chips that would >>>>> be good for this? I understand that I would need to divide by a >>>>> decimal value of 2.5 for the loop. >>>> PLLs a those low frequencies are real slow if you need some 'jitter >>>> free' output. >>>> >>>> Square waves have only odd harmonics. You could square up your 24 Hz, >>>> apply it to a narrow 120Hz BPF, then divide by two. >>>> >>>> -- >>>> Thanks, >>>> Fred. >>> The 24Hz is square. What would I use for a BP filter at such a LF >>> without having a very large inductor? >>> >>> Chris >> Make that an active filter. Only Rs and Cs, and at that low frequency, >> any opamp will nicely do. > > Caution: At such low frequencies, capacitor dissipation can play a > critical role in screwing up active filter performance. > > Clear back in the early '70's, while designing telephone filters I > discovered you can negate dissipation factor by making your > integrators such... > > http://analog-innovations.com/SED/StateVariableFilter(P+1).pdf > > Paste rather than just click, Agent doesn't like parentheses in a URL. > I don't know about the behavior of other readers. > > ...Jim Thompson SeaMonkey worked like a champ!
Re: 24Hz to 60Hz PLL? - MooseFET - 2010-02-14 11:10:00
On Feb 13, 12:31=A0pm, Chris <christopher.man...@gmail.com> wrote: > On Feb 13, 10:14=A0am, MooseFET <kensm...@rahul.net> wrote: > > > > > On Feb 13, 8:20=A0am, Vladimir Vassilevsky <nos...@nowhere.com> wrote: > > > > MooseFET wrote: > > > > On Feb 12, 3:01 pm, Vladimir Vassilevsky <nos...@nowhere.com> wrote= : > > > > >>Chris wrote: > > > > >>>I need to make a PLL that slaves to a 24Hz square wave. =A0The out= put of > > > >>>the loop would be a 60Hz square wave. =A0Any CMOS level chips that= would > > > >>>be good for this? =A0I understand that I would need to divide by a > > > >>>decimal value of 2.5 for the loop. > > > > >>Use a PIC. > > > > > No, the 8051 is the right processor for this. > > > > Personally I despise PICs. However PIC became a generic word for any > > > small microcontroller. Once a customer asked me if I work with PIC > > > controllers made by AVR company. > > > The PIC isn't all that bad. =A0It is just a little weirder than it > > needed > > to be. =A0I think part of it is because they did'nt think through the > > step > > to the next larger size. > > > When they designed the assembler for it, they compounded the > > weirdness. > > Given what it can do, a assembler that took expressions like: > > > =A0 =A0A +=3D Variable > > =A0 =A0Variable +=3D A > > > would have made it easier to read. > > > > Vladimir Vassilevsky > > > DSP and Mixed Signal Design Consultanthttp://www.abvolt.com > > Well the reason I am straying away from the MCU idea is that I really > want to just finish the project. =A0I am doing it in my spare time. =A0If > I could program it in about the same amount of time it would take me > to put together the aforementioned list of parts, then I am all ears. > However, never having messed around with programing a chip before, I > am thinking this could take another couple of dozen hours to > accomplish the task (factoring in a learning curve). > > However, if you guys think that the signal from my design would be too > jittery to be useful than I guess I don't have a choice, but to take > the MCU route. Since you only need to work over a very narrow range, you can use a crystal in the VCO part of the PLL. If you hunt among the frequencies you can get from digikey, I think you will easily find one that you can pull onto a power of two times 60Hz. A very simple flip-flop based phase detector can get a low jitter correction signal. A slightly more complex on based on some tristating can get you even lower. Enable the circuit output just before the "expected" rise of the 24Hz Follow the 24Hz input until after the "expected" rise. The "expected" value is a small number of clock cycles of the crystal. This can either be picked by the designer or learned by the circuit by decrementing the width until it just brackets the rise or incrementing if the rise goes outside the expected band. This method has the noise rejection characteristics of the XOR method for the case where there is a small noise in the input. It doesn't have a gain change as you go through the perfectly aligned case. This means that you can use a more extreme filter than the flip-flop case normally allows. > > Thanks, > Chris
Re: 24Hz to 60Hz PLL? - Jim Thompson - 2010-02-14 11:54:00
On Sat, 13 Feb 2010 22:14:15 -0500, Phil Hobbs <p...@electrooptical.net> wrote: >On 2/13/2010 9:08 PM, Jim Thompson wrote: >> On Sat, 13 Feb 2010 20:36:35 -0500, Phil Hobbs >> <p...@electrooptical.net> wrote: >> >>> On 2/13/2010 5:39 PM, Jim Thompson wrote: >>>> On Sat, 13 Feb 2010 14:16:57 -0800, John Larkin >>>> <j...@highNOTlandTHIStechnologyPART.com> wrote: [snip] >>>> >>>> John's last paragraph is absolutely correct... Ron Treadway and I >>>> designed it to be that way :-P >>>> >>>> ...Jim Thompson >>> >>> So how come you put that stupid deadband in there? ;) >>> >>> Cheers >>> >>> Phil Hobbs >> >> That's a mismatched delay issue. Later versions have that "fixed" by >> overlapping the U/D outputs. >> >> ...Jim Thompson > >Sort of hard to fix when the pulse goes completely away--with a given >slew rate, there's some range in which both the height and width of the >pulse depend on the phase error--which produces a flat spot in the >V(phi) curve. Or do the fixed versions pulse high, pulse low, and then >go tri-state at zero phase error? That would still give some ripple, >but that's a big improvement over deadbands. The "fixed" version output current pulses of a minimum width. > >Any part numbers with the fixed version? That caused me grief as a >youth, till I realized I could just use a resistor to ground to move the >set point a bit away from phi=0. AFAIK only in custom ASIC's. > >Thanks > >Phil Hobbs ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.