On Fri, 6 Nov 2009 10:26:46 -0800 (PST), Fred
<f...@gmail.com> wrote:

>I see the Spin chip is 6 MIPS, at 48kHz sample rate that only allows
>about 125 instruction steps per sample.  I was thinking of some thin
>with at least 30 MIPS.
>
>I see those Silicon Labs devices run at 50 and 100 MIPS, that would
>allow a higher sampling rate.  Other thatn that they seem overly
>capable.
>
>I only need 1 ADC input and 1 DAC output, and whatever I/O necessary
>to support table data if used.
>
>Regards,
>
>Fred
>
>
>
>On Nov 6, 12:28 pm, ChrisQ <m...@devnull.com> wrote:
>> krw wrote:
>>
>> > IOW, pretty trivial stuff.  I'd likely use an 8051 for that too (and
>> > pass the crap job off to the firmware group ;-).
>>
>> In my small company, I *am* the firmware group, and think software
>> design far more than hardware these days :-).
>>
>>
>>
>> > Nonsense.  I have two solutions (one Actel FPGA and the other an
>> > Altera CPLD) for another pretty trivial problem, both under $2.50, =
no
>> > EPROM/flash required.
>>
>> Not so cheap in the uk in small quantities and more expensive than an
>> silabs 8051. Using a gate array, would still have needed the eprom, as
>> the sine tables wouldn't fit, whereas they just go in code space using
>> an mcu. I get other benefits like self test, an a-d for soft start,
>> voltage regulation, current limiting etc and a serial port for status
>> messaging. There's even a temp sensor on chip !. Makes a far more
>> capable product for a couple of weeks of software effort, which you
>> would need anyway using vhdl.
>>
>> As an aside and have no commercial interest, the Silicon Labs fast =
8051
>> series are quite amazing. They are typically 50 mips risc cored =
updates
>> of the 8051 architecture and the dev kits range from ~$100 down, with
>> all the hardware and dev tools. You can get started building and =
running
>> the simple demos out of the box within 30 minutes or so. I don't =
really
>> rate the 8051 architecture that highly, but the latest versions do a
>> good job even with everything written in C.
>>
>>
>>
>> >> So what complex problems are you solving with gate arrays and what
>> >> speeds ?...
>>
>> > My current "problem" is also pretty trivial[*], yet an FPGA (or =
CPLD,
>> > not sure which) still makes a lot more sense than yet another micro
>> > and piles more software complexity.
>>
>> I guess everything's software now, even hardware design, so if there's
>> not much difference in cost, it probably comes down to what you are =
most
>> familiar with in the end...
>>
>> Regards,
>>
>> Chris

A XO a 22V10 and an EPROM?

On Nov 8, 2:09 pm, "JosephKK"<quiettechb...@yahoo.com> wrote:
> On Fri, 6 Nov 2009 10:26:46 -0800 (PST), Fred
>
>
>
> <frederick.br...@gmail.com> wrote:
> >I see the Spin chip is 6 MIPS, at 48kHz sample rate that only allows
> >about 125 instruction steps per sample.  I was thinking of some thin
> >with at least 30 MIPS.
>
> >I see those Silicon Labs devices run at 50 and 100 MIPS, that would
> >allow a higher sampling rate.  Other thatn that they seem overly
> >capable.
>
> >I only need 1 ADC input and 1 DAC output, and whatever I/O necessary
> >to support table data if used.
>
> >Regards,
>
> >Fred
>
> >On Nov 6, 12:28 pm, ChrisQ <m...@devnull.com> wrote:
> >> krw wrote:
>
> >> > IOW, pretty trivial stuff.  I'd likely use an 8051 for that too (and
> >> > pass the crap job off to the firmware group ;-).
>
> >> In my small company, I *am* the firmware group, and think software
> >> design far more than hardware these days :-).
>
> >> > Nonsense.  I have two solutions (one Actel FPGA and the other an
> >> > Altera CPLD) for another pretty trivial problem, both under $2.50, no
> >> > EPROM/flash required.
>
> >> Not so cheap in the uk in small quantities and more expensive than an
> >> silabs 8051. Using a gate array, would still have needed the eprom, as
> >> the sine tables wouldn't fit, whereas they just go in code space using
> >> an mcu. I get other benefits like self test, an a-d for soft start,
> >> voltage regulation, current limiting etc and a serial port for status
> >> messaging. There's even a temp sensor on chip !. Makes a far more
> >> capable product for a couple of weeks of software effort, which you
> >> would need anyway using vhdl.
>
> >> As an aside and have no commercial interest, the Silicon Labs fast 8051
> >> series are quite amazing. They are typically 50 mips risc cored updates
> >> of the 8051 architecture and the dev kits range from ~$100 down, with
> >> all the hardware and dev tools. You can get started building and running
> >> the simple demos out of the box within 30 minutes or so. I don't really
> >> rate the 8051 architecture that highly, but the latest versions do a
> >> good job even with everything written in C.
>
> >> >> So what complex problems are you solving with gate arrays and what
> >> >> speeds ?...
>
> >> > My current "problem" is also pretty trivial[*], yet an FPGA (or CPLD,
> >> > not sure which) still makes a lot more sense than yet another micro
> >> > and piles more software complexity.
>
> >> I guess everything's software now, even hardware design, so if there's
> >> not much difference in cost, it probably comes down to what you are most
> >> familiar with in the end...
>
> >> Regards,
>
> >> Chris
>
> A XO a 22V10 and an EPROM?

I presume you mean a Programmable Logic Array.  I'm clueless about
them as well as FPGAs.  I lack any idea of how the arrays would/could
be programmed to do my non-linear transform.